Search Verilog UART, 300 result(s) found

Address-data bus

This includes Verilog code for an address-data bus(ad bus) for a cpu. The address-data bits are of 16-bit....

Verilog float calculate

This code is used in Verilog, to calculate 2 float numbers,which to be calculated nubmer are all32 bits,it can be used....

UART Verilog

8b10b_Encoder -- Encoder VHDL files and Proj Nav. project file-- Note: This directory should be used for simulation        of both the encoder and decoder logic\8b10b_Decoder -- Decoder VHDL files and Proj Nav. project file...

verification of an UART protocal

A universal asynchronous receiver/transmitter, abbreviated UART /ˈjuːɑːrt/, is a computer hardware device that translates data between parallel and serialforms. UARTs are commonly used in conjunction with communication standards such as TIA (form...

Use Verilog HDL to realize common UART serial communications procedures, proven success

In the ISE General serial communication program developed by using programming language is the Verilog HDL language, using a FIFO, experiments have been carried out by suitable for Verilog beginners, welcomed the exchange of learning....

PS2_Verilog PS2 interface, new to FPGA is a good choice

PS2_Verilog PS2 interface, is a good choice for new to FPGA, PS2_Verilog PS2 interface, new to FPGA is a good choice...

Verilog Code for Synchronous FIFO and Asynchronous FIFO using Gray counter

Verilog Code is wirtten for Synchronous FIFO is a First-In-First-Out memory queue with control logic that manages the read and write pointers, generates status flags, and provides optional handshake signals for interfacing with the user logic. An asynchronous FIFO refers to...

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