Search verilog hdl,UART, 300 result(s) found

SDRAM Controller verilog source code

SDRAM core written using verilog hdl source code, test application-I used to write verilog hdl source of SDRAM core, the test application. Tested, stable use. If there is another bug or tests are not complete, you can email the original author. SDRAM core written using verilog hdl source code, test...

verilog Code for 8 bit array multiplier

I have written verilog for 8 bit array multiplier . Accepts two 8 bit numbers and gives 16 bit result....

Booth multiplier in verilog

This file describes the code for booth multiplier in verilog. the source code is simulated and verified for better results...

The implementation of Viterbi encoder and decoder VLSI

Application background Forward Error Correction techniques are utilized for correction of errors at the receiver end. It is well known that data transmissions over wireless channels are affected by attenuation, distortion interference and noise, which affect the receiver’s ability to receive...

verilog test image

verilog language the raw test images, color, gradient, grayscale, and moving still....

a processing unit of risc_spm

a processing unit of risc_spm  u can caculate some easy operations with its stored program.....

串口FIFO接口设计

本设计基于RS232进行了一个串口模块的设计,另外把一个FIFO加入其中,使得串口可以通过先进先出的模式进行数据的传输。...

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