Search verilog, 300 result(s) found

4 bit ripple counter

This includes verilog code for a 4-bit ripple counter, coded on Xilinx ISE platform. Code is tested and good....

verilog DCT program

Discrete cosine transform DCT Testbench overall framework DCT Are most calculation-intensive piece of JPEG compression, image of the entire component image into 8  8 blocks, and input into a two-dimensional discrete cosine transform and realization of discrete cosine transform. DCT based on look...

verilog CODE FOR I2C SINGLE MASTER

I2C protocol is the intelligent communication protocol.It supports communication between multiple master and slaves.However i have designed verilog code for single master only....

Write a signed 4-bit Adder/Subtractor verilog description.

Application backgroundWrite a verilog description for a 4-bit signed adder/subtracter. The module definition is : module add4(cout, sum, a, b, cin, reset, clk, add) input [3:0] a, b; input cin, reset, clk, add; // add=1/0 denotes addition/subtraction output [3:0] sum; output cout; . . ....

The implementation of Viterbi encoder and decoder VLSI

Application background Forward Error Correction techniques are utilized for correction of errors at the receiver end. It is well known that data transmissions over wireless channels are affected by attenuation, distortion interference and noise, which affect the receiver’s ability to receive...

FGPA, verilog, Siga-S16, Xilinx

Application background  verilog; FPD version of the teaching! I will continue to upload Xilinx development board can use some of the procedures, for beginners FPGA friends can come in to see!!Key TechnologyMainly for beginners FPGA friends upload information, and then the source code will be tra...

32 shifter verilog FPGA bit

Application background32 bit digital shifter, which can be used for the implementation of the multiplierKey Technology32 bit digital shift device, the use of the way to check the tender, based on FPGA and verilog language...

verilog prepared with the USB2.0 source code

USB2.0 communication module based on Hdl verilog language....

verilog CRC_16

Vivado verilog language under project CRC_16 parallel input byte length, it is possible to find out, the checksum of the data, width is 512 bytes of the code to the data source, can modify the length, measuring actual project ~ ~ ~...

verilog Code for Synchronous FIFO and Asynchronous FIFO using Gray counter

verilog Code is wirtten for Synchronous FIFO is a First-In-First-Out memory queue with control logic that manages the read and write pointers, generates status flags, and provides optional handshake signals for interfacing with the user logic. An asynchronous FIFO refers to...

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