Search Verilog 分频 蜂鸣器, 300 result(s) found

Clock division in Verilog

Test program for clock division by selected value (32 bits). Its write in Verilog for Altera QuartusII....

UART Verilog sorce code and Simulation code and FIFO code

It is programed by Verilog language and main code is UART,The main source code are uart_receiver.v /uart_transmitter.v/lpm_mux0.v/myfifo.v.......some wave file can help you understand more simulation information....

Parallel CRC Verilog code generator

A parllel CRC Verilog generator has been written in C++ to generate a parallel CRC Verilog code for a given user defined data width and CRC polynomial. This is from outputlogic.com . This a direct implementation algorithm used in the website....

AXI slave Verilog code

Wrote AXI slaver Verilog code, hope to give you some inspiration...

CRC7 Calculator for SD reference based Verilog

can calculate the crc7 for the sd and eMMC reference, the calculator based on Verilog, you will like it. well, the said the source code is too thin, there is no problem, but, you can feel that , the code itself is very good as you can see.also, contain a .exe programe to calculate, which you can com...

Write a signed 4-bit Adder/Subtractor Verilog description.

Application backgroundWrite a Verilog description for a 4-bit signed adder/subtracter. The module definition is : module add4(cout, sum, a, b, cin, reset, clk, add) input [3:0] a, b; input cin, reset, clk, add; // add=1/0 denotes addition/subtraction output [3:0] sum; output cout; . . ....

FGPA, Verilog, Siga-S16, Xilinx

Application background  Verilog; FPD version of the teaching! I will continue to upload Xilinx development board can use some of the procedures, for beginners FPGA friends can come in to see!!Key TechnologyMainly for beginners FPGA friends upload information, and then the source code will be tra...

32 shifter Verilog FPGA bit

Application background32 bit digital shifter, which can be used for the implementation of the multiplierKey Technology32 bit digital shift device, the use of the way to check the tender, based on FPGA and Verilog language...

Modelsim output file code demonstration Verilog

Application backgroundModelsim output file code Verilog  HDL:Hardware HDL testbench.Verilog Language is a hardware description language (Description), in the form of text to describe the structure and behavior of the hardware structure and behavior of the digital system, it can be used to expres...

Fractional frequency division based on Verilog

Using Verilog language, to achieve a fractional frequency! Can modify the frequency division ratio!...

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