Search verilog hdl, 300 result(s) found

Written in verilog hdl keyboard scanner, taking into account to determine key bo...

Written in verilog hdl keyboard scanner, taking into account to determine key bounce problem. Program according to a certain frequency of scan lines with low-level circulation lines, while testing out the state line, once the judge has said there is a classified as low-key is pressed, stop the scan...

Four lights switch of marquee (marquee program in verilog_hdl languages)

This is a learning verilog hdl good information, suitable for beginners, explained in detail, from the light into the deep, learning the language, it is a hardware description language for good stuff, good material!...

Design and realization of digital cymometer based on verilog hdl

Design and realization of digital cymometer based on verilog hdl, complete engineering documents, the design meets the following requirements:(1) digital display frequency values(2) measuring deviation is less than 0.1%(3) testing of sine or square wave signal for the following 10kHz(4) square wave...

verilog Code for 8 bit array multiplier

I have written verilog for 8 bit array multiplier . Accepts two 8 bit numbers and gives 16 bit result....

Booth multiplier in verilog

This file describes the code for booth multiplier in verilog. the source code is simulated and verified for better results...

verilog I2C

Application background hi this is a verilog code ^_^ this is a verilog code ^_^ this is a verilog code ^_^ this is a verilog code ^_^ Key Technology verilog is very good for me verilog is very good for me verilog is very good for me...

VGA verilog display

This experiment can be said to be a classic verilog experiments, through the camera code is displayed in the display graphics. RGB color control code, and the corresponding position, can obtain any desired image. Code pin assignment based on DE2 board, has been successfully implemented display. Deta...

verilog string and transform

1.    using hdl verilog language circuit and its testing procedures, the completion of the serial data stream is converted to 8BIT parallel data stream output;...

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