Search Verilog 分频 蜂鸣器, 300 result(s) found

4 bit ripple counter

This includes Verilog code for a 4-bit ripple counter, coded on Xilinx ISE platform. Code is tested and good....

The implementation of Viterbi encoder and decoder VLSI

Application background Forward Error Correction techniques are utilized for correction of errors at the receiver end. It is well known that data transmissions over wireless channels are affected by attenuation, distortion interference and noise, which affect the receiver’s ability to receive...

Serial port transceiver protocols based on Verilog

Serial transceiver based on Verilog programs using combinational and sequential logic written, easy to modify!...

A FIR filter written in Verilog,

This code achieved a FIR filter, combined Matlab on data for for validation, last with modesim on prepared of code for simulation, eventually with MATLAB and FPGA achieved a function normal of FIR low pass filter, here with source code, and with Verilog code prepared, has is big of reference role fo...

CPU32_adder

introduce the Verilog language and use this to implement the calculation two 32-bit numbers including the multiplication.  In the codes, I input my CWID and 41411 to validate the function. you can change the HEX files to calculate different value. Architecture: Carry-Ripple+Carry-Skip....

CPU32_adder

introduce the Verilog language and use this to implement the calculation two 32-bit numbers including the multiplication.  In the codes, I input my CWID and 41411 to validate the function. you can change the HEX files to calculate different value. Architecture: Carry-Ripple+Carry-Skip....

CPU32_adder

introduce the Verilog language and use this to implement the calculation two 32-bit numbers including the multiplication.  In the codes, I input my CWID and 41411 to validate the function. you can change the HEX files to calculate different value. Architecture: Carry-Ripple+Carry-Skip....

16-point FFT Verilog code

Verilog implementation of 16-point FFT can be implemented in the FPGA, hardware acceleration...

Verilog Code for Synchronous FIFO and Asynchronous FIFO using Gray counter

Verilog Code is wirtten for Synchronous FIFO is a First-In-First-Out memory queue with control logic that manages the read and write pointers, generates status flags, and provides optional handshake signals for interfacing with the user logic. An asynchronous FIFO refers to...

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