Search verilog hdl, 300 result(s) found

In this case is a convolutional code on a simple algorithm, using verilog hdl la...

In this case is a convolutional code on a simple algorithm, using verilog hdl language, the entire document, including the method of deconvolution of the whole project....

a verilog hdl language used in the preparation of multi

a verilog hdl language used in the preparation of multi-channel demultiplexer...

Taiwan verilog hdl hardware description language, suitable for those who have th...

Taiwan verilog hdl hardware description language, suitable for those who have the basis of...

verilog Modified Baugh Wooley 8 x 8 Multiplier

This code is for Modified Baugh Wooley Multiplier with multiplier strength-8 x 8, and written in verilog Gate level or structural port mapping method and test verified with  functional simulation from Xilinx and Altera Quartus II...

Simple digital Zhong Chengxu (based on ALTERA quartusII)

A simple digital clock procedures, can achieve 24 hours, the whole point of time, accurate timing clock correction, clock and reset function...

a processing unit of risc_spm

a processing unit of risc_spm  u can caculate some easy operations with its stored program.....

基于fpga的SPI接口实现

本工程是基于Altera Cyclone系列的FPGA来实现的SPI接口,使用verilog代码编写,能够进行 8位、 16位 、 32位数据传输的可选操作。...

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