Search verilog hdl, 300 result(s) found

verilog 经典实例,完整源码与大家分享

verilog classic example of a complete source to share with you...

Elliptic-curve cryptography verilog code

Elliptical encryption algorithms (ECC) is a public key encryption system, originally proposed by Miller and Koblitz, whom in 1985, its mathematical basis is the use of rational points on elliptic curves Abel ellipse on the additive group of the computational difficulty of the discrete logarithm.Stud...

PipelineCPU_5stage_verilog

Pipeline CPU with 5 stage: IF,ID,EX MEM,WB. Every module has a test bench. It contains a whole ISE project. You can run it directly. ROM module has pre-stored instruction as an instance....

FPGA_ elevator controller

This code is mainly based on FPGA simulation elevator controllers. The Spartan3E design for Xinlinx Company  250   as a platform based LCD1602 peripherals and send RS232 serial port peripheral, was successfully carried out on a three-story elevator simulation of real-time operational statu...

15 job design of 16 bit reversible logic ALU

Application backgroundReversible logic is one of the emerging technologies having promising applications in quantum computing. This project will deal with the design of a 16 bit reversible Arithmetic Logic Unit (ALU) with 15 operations is presented by making use of Double Peres gate, Fredk...

The design of the hdl verilog for the candy dispenser

Application background Candy Vending machine is an innovative industry, designing and producing machines, with the latest technological improvements and provides refreshment, in the way of dispensing different candies, providing a moment of pleasure amongst colleagues, while talking shop. At Au...

design of full adder using verilog hdl

A full adder adds binary numbers and accounts for values carried in as well as out. A one-bit full adder adds three one-bit numbers, often written as A, B, and Cin; A and B are the operands, and Cin is a bit carried in from the previous less sig...

ADPLL(All Digital Phase Locked Loop)

This code is designed for all digital phase locked loop(ADPLL). Code is written in verilog language. Software used for implementing the code is Xilinx 14.7....

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