Search Verilog UART, 300 result(s) found


it is the program that is used to configure DSP TMS320C6713 comnunicate with PC through UART. the program is simple but it is neccessary for people who are beginner. hope that when beginner read this code they will have overview of DSP and know the way to use it effectively....

Verilog Code for 8 bit array multiplier

I have written Verilog for 8 bit array multiplier . Accepts two 8 bit numbers and gives 16 bit result....

Booth multiplier in Verilog

This file describes the code for booth multiplier in Verilog. the source code is simulated and verified for better results...

Verilog temperature control commands

Verilog temperature control command realizes the temperature acquisition and operation, as well as other control  commands very well...

Verilog code FIFO

FIFO is a First-In-First-Out memory queue with control logic that managesthe read and write operations, generates status flags, and provides optionalhandshake signals for interfacing with the user logic. It is often used tocontrol the flow of data between source and destination. FIFO can beclassifie...

Verilog Modified Baugh Wooley 8 x 8 Multiplier

This code is for Modified Baugh Wooley Multiplier with multiplier strength-8 x 8, and written in Verilog Gate level or structural port mapping method and test verified with  functional simulation from Xilinx and Altera QUARTus II...

UART Verilog

Zip file contains the top-level files and test files. Finished sending and receiving. Delivery module and receiver modules are described in the file at the top level. To define several different communication speed. Send and receive rules are 10 bit is sent at a time. Entirely on serial communicatio...

VGA Verilog display

This experiment can be said to be a classic Verilog experiments, through the camera code is displayed in the display graphics. RGB color control code, and the corresponding position, can obtain any desired image. Code pin assignment based on DE2 board, has been successfully implemented display. Deta...


SPI slave interface protocol, based on Verilog, debugging available...

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