Search verilog hdl,UART, 300 result(s) found

verilog hdl 135 cases Guide : verilog hdl language similar to the C language, to...

verilog hdl 135 cases Guide : verilog hdl language similar to the C language, to facilitate learning. This document with the source code, 3-6...

verilog hdl for Half Adder, Full Subtractor, Half Subtractor and 2x4 decoder.

verilog hdl for Half Adder, Full Subtractor, Half Subtractor and 2x4 decoder....

verilog code FIFO

FIFO is a First-In-First-Out memory queue with control logic that managesthe read and write operations, generates status flags, and provides optionalhandshake signals for interfacing with the user logic. It is often used tocontrol the flow of data between source and destination. FIFO can beclassifie...

UART TRANSMITTER

UART Transmitter with a 8 bit data bus and 8 bit address bus.Transmitter FIFO is included and Transmitter State Machine is including the states: Idle, Start of Transmission, Stop of Transmission,  Actual data transfer.UART Transmitter can be connect to any UART Receiver with configurable data a...

UART-gen.rar

UART-gen.rar, is about 1 asynchronous communication in the internal loop test is no problem, the logic should be basically no problem. But if it turns out to be an external communication, look at the data inputs and outputs....

UART module verilog codes and guidance

verilog codes of UART modules and guidances of UART...

UART_verilog

UART_verilog,,,,,,UART_verilogUART_verilogUART_verilogUART_verilogUART_verilogUART_verilogUART_verilogUART_verilog...

prev 1 2 3 4 5 6 7 8 9 10 ... 30 next
Sponsored links

LOGIN

Don't have an account? Register now
Need any help?
Mail to: support@codeforge.com

切换到中文版?

CodeForge Chinese Version
CodeForge English Version

Where are you going?

^_^"Oops ...

Sorry!This guy is mysterious, its blog hasn't been opened, try another, please!
OK

Warm tip!

CodeForge to FavoriteFavorite by Ctrl+D