Search UART module Verilog guidance, 300 result(s) found

UART Verilog sorce code and Simulation code and FIFO code

It is programed by Verilog language and main code is UART,The main source code are UART_receiver.v /UART_transmitter.v/lpm_mux0.v/myfifo.v.......some wave file can help you understand more simulation information....


UART Transmitter with a 8 bit data bus and 8 bit address bus.Transmitter FIFO is included and Transmitter State Machine is including the states: Idle, Start of Transmission, Stop of Transmission,  Actual data transfer.UART Transmitter can be connect to any UART Receiver with configurable data a...

Video decoding of RGB YUV module (Verilog)

Application backgroundVideo decoding of RGB YUV module (Verilog)Video decoding of RGB YUV module (Verilog)Video decoding of RGB YUV module (Verilog)Video decoding of RGB YUV module (Verilog)Video decoding of RGB YUV module (Verilog)...


UART-gen.rar, is about 1 asynchronous communication in the internal loop test is no problem, the logic should be basically no problem. But if it turns out to be an external communication, look at the data inputs and outputs....

UART module Verilog codes and guidance

Verilog codes of UART modules and guidances of UART...

UART send and receive Verilog detailed notes

UART receive Verilog files contain detailed notes engineering baud rate setting Applied to Verilog scholars and engineers use...




UART 串口 Verilog 含testbench qUARTus工程 全双工 发送模块 接受模块...

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