sum.v ( File view )

From:H264 Verilog
  • By culourwq 2016-05-23
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			//--------------------------------------------------------------------------------------------------
// Design    : nova
// Author(s) : Ke Xu
// Email	   : eexuke@yahoo.com
// File      : sum.v
// Generated : Oct 29, 2005
// Copyright (C) 2008 Ke Xu                
//-------------------------------------------------------------------------------------------------
// Description 
// Sum module for residual + prediction
// Including output transpose and Intra_mbAddrB_RAM write control
//-------------------------------------------------------------------------------------------------

// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "nova_defines.v"

module sum (clk,reset_n,slice_data_state,residual_state,TotalCoeff,curr_CBPLuma_IsZero,CodedBlockPatternChroma,
	curr_DC_IsZero,curr_DC_scaled,gclk_pred_output,gclk_blk4x4_sum,trigger_blk4x4_rec_sum,
	IQIT_output_0, IQIT_output_1, IQIT_output_2, IQIT_output_3,
	IQIT_output_4, IQIT_output_5, IQIT_output_6, IQIT_output_7,
	IQIT_output_8, IQIT_output_9, IQIT_output_10,IQIT_output_11,
	IQIT_output_12,IQIT_output_13,IQIT_output_14,IQIT_output_15,
	mb_type_general,Intra4x4_predmode,Intra16x16_predmode,Intra_chroma_predmode,
	Intra_pred_PE0_out,Intra_pred_PE1_out,Intra_pred_PE2_out,Intra_pred_PE3_out,blk4x4_intra_calculate_counter,
	Inter_pred_out0,Inter_pred_out1,Inter_pred_out2,Inter_pred_out3,blk4x4_inter_calculate_counter,Inter_chroma2x2_counter,
	Inter_blk4x4_pred_output_valid,mv_below8x8_curr,pos_FracL,mb_num_v,mb_num_h,LowerMB_IsSkip,
	
	end_of_one_blk4x4_sum,blk4x4_sum_counter,blk4x4_rec_counter,
	blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out,
	sum_right_column_reg,blk4x4_rec_counter_2_raster_order,
	blk4x4_pred_output0, blk4x4_pred_output1, blk4x4_pred_output2,
	blk4x4_pred_output4, blk4x4_pred_output5, blk4x4_pred_output6,
	blk4x4_pred_output8, blk4x4_pred_output9, blk4x4_pred_output10,
	blk4x4_pred_output12,blk4x4_pred_output13,blk4x4_pred_output14,
	Intra_mbAddrB_RAM_wr,Intra_mbAddrB_RAM_wr_addr,Intra_mbAddrB_RAM_din
	);
	input clk,reset_n;
	input [3:0] slice_data_state;
	input [3:0] residual_state;
	input [4:0] TotalCoeff;
	input curr_CBPLuma_IsZero;
	input [1:0] CodedBlockPatternChroma;
	input curr_DC_IsZero;
	input [8:0] curr_DC_scaled;
	input gclk_pred_output;
	input gclk_blk4x4_sum;
	input trigger_blk4x4_rec_sum;
	//residual from IQIT
	input [8:0] IQIT_output_0, IQIT_output_1, IQIT_output_2, IQIT_output_3;
	input [8:0] IQIT_output_4, IQIT_output_5, IQIT_output_6, IQIT_output_7;
	input [8:0] IQIT_output_8, IQIT_output_9, IQIT_output_10,IQIT_output_11;
	input [8:0] IQIT_output_12,IQIT_output_13,IQIT_output_14,IQIT_output_15;
	//Intra prediction output
	input [3:0] mb_type_general;
	input [3:0]	Intra4x4_predmode;
	input [1:0] Intra16x16_predmode;
	input [1:0] Intra_chroma_predmode;
	input [7:0] Intra_pred_PE0_out,Intra_pred_PE1_out,Intra_pred_PE2_out,Intra_pred_PE3_out;
	input [2:0] blk4x4_intra_calculate_counter;
	//Inter prediction output
	input [7:0] Inter_pred_out0,Inter_pred_out1,Inter_pred_out2,Inter_pred_out3;
	input [1:0] Inter_blk4x4_pred_output_valid;
	input mv_below8x8_curr;
	input [3:0] pos_FracL;
	input [3:0] blk4x4_inter_calculate_counter;
	input [1:0] Inter_chroma2x2_counter;
	input [3:0] mb_num_h,mb_num_v;
	input LowerMB_IsSkip;
	
	output end_of_one_blk4x4_sum;
	output [2:0] blk4x4_sum_counter;
	output [4:0] blk4x4_rec_counter;
	output [7:0] blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out;
	output [23:0] sum_right_column_reg;
	output [4:0] blk4x4_rec_counter_2_raster_order;
	output [7:0] blk4x4_pred_output0, blk4x4_pred_output1, blk4x4_pred_output2;
	output [7:0] blk4x4_pred_output4, blk4x4_pred_output5, blk4x4_pred_output6;
	output [7:0] blk4x4_pred_output8, blk4x4_pred_output9, blk4x4_pred_output10;
	output [7:0] blk4x4_pred_output12,blk4x4_pred_output13,blk4x4_pred_output14;
	output Intra_mbAddrB_RAM_wr;
	output [6:0] Intra_mbAddrB_RAM_wr_addr;
	output [31:0] Intra_mbAddrB_RAM_din; 
		
	reg [2:0] blk4x4_sum_counter;
	reg [4:0] blk4x4_rec_counter;
	reg [4:0] blk4x4_rec_counter_2_raster_order;
	reg [23:0] sum_right_column_reg;
		
	reg [7:0] blk4x4_pred_output0, blk4x4_pred_output1, blk4x4_pred_output2, blk4x4_pred_output3;
	reg [7:0] blk4x4_pred_output4, blk4x4_pred_output5, blk4x4_pred_output6, blk4x4_pred_output7;
	reg [7:0] blk4x4_pred_output8, blk4x4_pred_output9, blk4x4_pred_output10,blk4x4_pred_output11;
	reg [7:0] blk4x4_pred_output12,blk4x4_pred_output13,blk4x4_pred_output14,blk4x4_pred_output15;
	

	always @ (posedge gclk_pred_output or negedge reset_n)
		if (reset_n == 1'b0)
			begin blk4x4_pred_output0  <= 0; blk4x4_pred_output1 <= 0; blk4x4_pred_output2  <= 0; blk4x4_pred_output3  <= 0; 
				  blk4x4_pred_output4  <= 0; blk4x4_pred_output5 <= 0; blk4x4_pred_output6  <= 0; blk4x4_pred_output7  <= 0; 
				  blk4x4_pred_output8  <= 0; blk4x4_pred_output9 <= 0; blk4x4_pred_output10 <= 0; blk4x4_pred_output11 <= 0;
				  blk4x4_pred_output12 <= 0; blk4x4_pred_output13<= 0; blk4x4_pred_output14 <= 0; blk4x4_pred_output15 <= 0; end
		else if (blk4x4_intra_calculate_counter != 0)
			begin
				//Intra4x4DC or chromaDC intra prediction:output valid only at cycle3 by PE0
				if ((mb_type_general[3:2] == 2'b11 && blk4x4_rec_counter < 16 && Intra4x4_predmode == `Intra4x4_DC) ||
            (mb_type_general[3]   == 1'b1  && blk4x4_rec_counter > 15 && Intra_chroma_predmode == `Intra_chroma_DC))
					begin 
						if (blk4x4_intra_calculate_counter == 3'd3) //Intra4x4DC or chromaDC completes calculation at cycle3 by PE0
							begin
								blk4x4_pred_output0  <= Intra_pred_PE0_out; blk4x4_pred_output1  <= Intra_pred_PE0_out;
								blk4x4_pred_output2  <= Intra_pred_PE0_out; blk4x4_pred_output3  <= Intra_pred_PE0_out;
								blk4x4_pred_output4  <= Intra_pred_PE0_out; blk4x4_pred_output5  <= Intra_pred_PE0_out;
								blk4x4_pred_output6  <= Intra_pred_PE0_out; blk4x4_pred_output7  <= Intra_pred_PE0_out;
								blk4x4_pred_output8  <= Intra_pred_PE0_out; blk4x4_pred_output9  <= Intra_pred_PE0_out;
								blk4x4_pred_output10 <= Intra_pred_PE0_out; blk4x4_pred_output11 <= Intra_pred_PE0_out;
								blk4x4_pred_output12 <= Intra_pred_PE0_out; blk4x4_pred_output13 <= Intra_pred_PE0_out;
								blk4x4_pred_output14 <= Intra_pred_PE0_out; blk4x4_pred_output15 <= Intra_pred_PE0_out;
							end
					end
				//Intra16x16DC intra prediction:output valid only at cycle1 by PE0
				else if (mb_type_general[3:2] == 2'b10 && blk4x4_rec_counter < 16 && Intra16x16_predmode == `Intra16x16_DC)
					begin 
						if (blk4x4_rec_counter == 0 && blk4x4_intra_calculate_counter == 3'd1) 
							begin
								blk4x4_pred_output0  <= Intra_pred_PE0_out; blk4x4_pred_output1  <= Intra_pred_PE0_out;
								blk4x4_pred_output2  <= Intra_pred_PE0_out; blk4x4_pred_output3  <= Intra_pred_PE0_out;
								blk4x4_pred_output4  <= Intra_pred_PE0_out; blk4x4_pred_output5  <= Intra_pred_PE0_out;
								blk4x4_pred_output6  <= Intra_pred_PE0_out; blk4x4_pred_output7  <= Intra_pred_PE0_out;
								blk4x4_pred_output8  <= Intra_pred_PE0_out; blk4x4_pred_output9  <= Intra_pred_PE0_out;
								blk4x4_pred_output10 <= Intra_pred_PE0_out; blk4x4_pred_output11 <= Intra_pred_PE0_out;
								blk4x4_pred_output12 <= Intra_pred_PE0_out; blk4x4_pred_output13 <= Intra_pred_PE0_out;
								blk4x4_pred_output14 <= Intra_pred_PE0_out; blk4x4_pred_output15 <= Intra_pred_PE0_out;
							end
					end
				//Besides above DC intra prediction case,other intra prediction modes output valid from cycle4 ~ cycle1
				else
					case (blk4x4_intra_calculate_counter)
						3'd4:begin	blk4x4_pred_output0  <= Intra_pred_PE0_out; blk4x4_pred_output4  <= Intra_pred_PE1_out; 
									blk4x4_pred_output8  <= Intra_pred_PE2_out; blk4x4_pred_output12 <= Intra_pred_PE3_out;	end
						3'd3:begin	blk4x4_pred_output1  <= Intra_pred_PE0_out; blk4x4_pred_output5  <= Intra_pred_PE1_out; 
									blk4x4_pred_output9  <= Intra_pred_PE2_out; blk4x4_pred_output13 <= Intra_pred_PE3_out;	end
						3'd2:begin	blk4x4_pred_output2  <= Intra_pred_PE0_out; blk4x4_pred_output6  <= Intra_pred_PE1_out; 
									blk4x4_pred_output10 <= Intra_pred_PE2_out; blk4x4_pred_output14 <= Intra_pred_PE3_out;	end
						3'd1:begin	blk4x4_pred_output3  <= Intra_pred_PE0_out; blk4x4_pred_output7  <= Intra_pred_PE1_out; 
									blk4x4_pred_output11 <= Intra_pred_PE2_out; blk4x4_pred_output15 <= Intra_pred_PE3_out;	end
				   	endcase
			end
		//Inter luma prediction output store
		else if (Inter_blk4x4_pred_output_valid == 2'b01)
			begin
				if (pos_FracL == `pos_i || pos_FracL == `pos_k)
					case (blk4x4_inter_calculate_counter)
						4'd7:begin	blk4x4_pred_output0  <= Inter_pred_out0; blk4x4_pred_output4  <= Inter_pred_out1; 
									blk4x4_pred_output8  <= Inter_pred_out2; blk4x4_pred_output12 <= Inter_pred_out3;	end
						4'd5:begin	blk4x4_pred_output1  <= Inter_pred_out0; blk4x4_pred_output5  <= Inter_pred_out1; 
									blk4x4_pred_output9  <= Inter_pred_out2; blk4x4_pred_output13 <= Inter_pred_out3;	end
						4'd3:begin	blk4x4_pred_output2  <= Inter_pred_out0; blk4x4_pred_output6  <= Inter_pred_out1; 
									blk4x4_pred_output10 <= Inter_pred_out2; blk4x4_pred_output14 <= Inter_pred_out3;	end
						4'd1:begin	blk4x4_pred_output3  <= Inter_pred_out0; blk4x4_pred_output7  <= Inter_pred_out1; 
									blk4x4_pred_output11 <= Inter_pred_out2; blk4x4_pred_output15 <= Inter_pred_out3;	end
					endcase
				else
					case (blk4x4_inter_calculate_counter)
						4'd4:begin	blk4x4_pred_output0  <= Inter_pred_out0; blk4x4_pred_output4  <= Inter_pred_out1; 
									blk4x4_pred_output8  <= Inter_pred_out2; blk4x4_pred_output12 <= Inter_pred_out3;	end
						4'd3:begin	blk4x4_pred_output1  <= Inter_pred_out0; blk4x4_pred_output5  <= Inter_pred_out1; 
									blk4x4_pred_output9  <= Inter_pred_out2; blk4x4_pred_output13 <= Inter_pred_out3;	end
						4'd2:begin	blk4x4_pred_output2  <= Inter_pred_out0; blk4x4_pred_output6  <= Inter_pred_out1; 
									blk4x4_pred_output10 <= Inter_pred_out2; blk4x4_pred_output14 <= Inter_pred_out3;	end
						4'd1:begin	blk4x4_pred_output3  <= Inter_pred_out0; blk4x4_pred_output7  <= Inter_pred_out1; 
									blk4x4_pred_output11 <= Inter_pred_out2; bl
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Intra_pred_PE.sdf2.05 MB22-02-09|14:06
Intra_pred_PE.srd1.03 MB22-02-09|14:06
Intra_pred_PE.srm1.61 MB22-02-09|14:06
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syntmp0.00 B22-02-09|14:46
@inter_pred_reg_ctrl0.00 B24-02-09|15:26
@intra4x4_@pred@mode_decoding0.00 B21-02-09|17:50
@intra_pred_@p@e0.00 B24-02-09|15:27
@intra_pred_pipeline0.00 B26-02-09|11:49
@intra_pred_reg_ctrl0.00 B26-02-09|11:49
@intra_pred_top0.00 B22-02-09|21:56
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plane_@h@v_precomputation0.00 B26-02-09|11:49
plane_a_precomputation0.00 B26-02-09|11:49
plane_bc_precomputation0.00 B26-02-09|11:49
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...
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