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nova_tb.v ( File view )

From:H264 Verilog
  • By culourwq 2016-05-23
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			//--------------------------------------------------------------------------------------------------
// Design    : nova
// Author(s) : Ke Xu
// Email	   : eexuke@yahoo.com
// File      : nova_tb.v
// Generated : March 13,2006
// Copyright (C) 2008 Ke Xu                
//-------------------------------------------------------------------------------------------------
// Description 
// Testbench for nova
//-------------------------------------------------------------------------------------------------

// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "nova_defines.v"

module nova_tb;
	
	reg clk;
	reg reset_n;
	reg pin_disable_DF;
	reg freq_ctrl0;
	reg freq_ctrl1;
	
	wire BitStream_ram_ren;
	wire [16:0] BitStream_ram_addr; 
	wire [15:0] BitStream_buffer_input;
	wire [5:0] pic_num;
	wire [6:0] mb_num;
	
	wire [13:0] ext_frame_RAM0_addr;
	wire [31:0] ext_frame_RAM0_data;
	wire [13:0] ext_frame_RAM1_addr;
	wire [31:0] ext_frame_RAM1_data;
	wire [31:0] dis_frame_RAM_din;
	
	wire [15:0] temp;
	assign temp = dis_frame_RAM_din[15:0];
	
	//for debug only
	wire slice_header_s6;
	
	Beha_BitStream_ram Beha_BitStream_ram (
		.clk(clk),
		.BitStream_ram_ren(BitStream_ram_ren),
		.BitStream_ram_addr(BitStream_ram_addr),
		.BitStream_ram_data(BitStream_buffer_input)
		);
	ext_frame_RAM0_wrapper ext_frame_RAM0_wrapper (
		.clk(clk),
		.reset_n(reset_n),
		.ext_frame_RAM0_cs_n(ext_frame_RAM0_cs_n),
		.ext_frame_RAM0_wr(ext_frame_RAM0_wr),
		.ext_frame_RAM0_addr(ext_frame_RAM0_addr),
		.dis_frame_RAM_din(dis_frame_RAM_din),
		.ext_frame_RAM0_data(ext_frame_RAM0_data),
		.pic_num(pic_num),
		.slice_header_s6(slice_header_s6)
		);
	ext_frame_RAM1_wrapper ext_frame_RAM1_wrapper (
		.clk(clk),
		.reset_n(reset_n),
		.ext_frame_RAM1_cs_n(ext_frame_RAM1_cs_n),
		.ext_frame_RAM1_wr(ext_frame_RAM1_wr),
		.ext_frame_RAM1_addr(ext_frame_RAM1_addr),
		.dis_frame_RAM_din(dis_frame_RAM_din),
		.ext_frame_RAM1_data(ext_frame_RAM1_data),
		.pic_num(pic_num
...
...
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Name Size Date
Beha_BitStream_ram.v1.16 kB30-04-08|11:58
BitStream_buffer.v11.65 kB30-04-08|11:58
BitStream_controller.v25.60 kB30-04-08|11:58
bitstream_gclk_gen.v12.67 kB30-04-08|11:58
BitStream_parser_FSM_gating.v27.58 kB30-04-08|11:58
bs_decoding.v45.34 kB30-04-08|11:58
cavlc_consumed_bits_decoding.v1.85 kB30-04-08|11:58
cavlc_decoder.v10.33 kB30-04-08|11:58
CodedBlockPattern_decoding.v5.83 kB30-04-08|11:58
dependent_variable_decoding.v2.42 kB30-04-08|11:58
DF_mem_ctrl.v29.69 kB30-04-08|11:58
DF_pipeline.v33.65 kB30-04-08|11:58
DF_reg_ctrl.v15.94 kB30-04-08|11:58
DF_top.v7.41 kB30-04-08|11:58
end_of_blk_decoding.v2.82 kB30-04-08|11:58
exp_golomb_decoding.v6.17 kB30-04-08|11:58
ext_frame_RAM0_wrapper.v5.09 kB30-04-08|11:58
ext_frame_RAM1_wrapper.v5.10 kB30-04-08|11:58
ext_RAM_ctrl.v3.46 kB30-04-08|11:58
H.264.cr.mti2.20 kB28-02-09|13:54
H.264.mpf55.79 kB28-02-09|00:05
heading_one_detector.v2.51 kB30-04-08|11:58
hybrid_pipeline_ctrl.v10.79 kB30-04-08|11:58
Inter_mv_decoding.v93.25 kB30-04-08|11:58
Inter_pred_CPE.v3.74 kB30-04-08|11:58
Inter_pred_LPE.v23.87 kB30-04-08|11:58
Inter_pred_pipeline.v33.29 kB30-04-08|11:58
Inter_pred_reg_ctrl.v124.27 kB30-04-08|11:58
Inter_pred_sliding_window.v130.18 kB30-04-08|11:58
Inter_pred_top.v28.66 kB30-04-08|11:58
Intra4x4_PredMode_decoding.v14.99 kB30-04-08|11:58
Intra_pred_PE.v69.16 kB30-04-08|11:58
Intra_pred_pipeline.v32.46 kB24-02-09|22:46
Intra_pred_reg_ctrl.v36.37 kB30-04-08|11:58
Intra_pred_top.v14.40 kB30-04-08|11:58
IQIT.v32.48 kB30-04-08|11:58
level_decoding.v7.45 kB30-04-08|11:58
nC_decoding.v30.47 kB30-04-08|11:58
nova.v8.19 kB30-04-08|11:58
nova_defines.v12.10 kB30-04-08|11:58
nova_tb.v2.92 kB30-04-08|11:58
NumCoeffTrailingOnes_decoding.v25.79 kB30-04-08|11:58
pc_decoding.v10.34 kB30-04-08|11:58
QP_decoding.v2.31 kB30-04-08|11:58
ram_async_1r_sync_1w.v2.71 kB30-04-08|11:58
ram_sync_1r_sync_1w.v3.01 kB30-04-08|11:58
reconstruction.v22.49 kB30-04-08|11:58
rec_DF_RAM0_96x32.v18.23 kB30-04-08|11:58
rec_DF_RAM0_wrapper.v1.73 kB30-04-08|11:58
rec_DF_RAM1_96x32.v18.23 kB30-04-08|11:58
rec_DF_RAM1_wrapper.v1.73 kB30-04-08|11:58
rec_DF_RAM_ctrl.v6.42 kB30-04-08|11:58
rec_gclk_gen.v16.68 kB30-04-08|11:58
Intra_pred_PE.areasrr10.14 kB22-02-09|14:06
Intra_pred_PE.edn2.76 MB22-02-09|14:06
Intra_pred_PE.fse0.00 B22-02-09|14:06
Intra_pred_PE.sdf2.05 MB22-02-09|14:06
Intra_pred_PE.srd1.03 MB22-02-09|14:06
Intra_pred_PE.srm1.61 MB22-02-09|14:06
Intra_pred_PE.srr34.82 kB22-02-09|14:06
Intra_pred_PE.srs102.69 kB22-02-09|14:06
Intra_pred_PE.tlg418.00 B22-02-09|14:06
Intra_pred_PE_sdc.sdc310.00 B22-02-09|14:06
Intra_pred_PE.msg0.00 B22-02-09|14:46
Intra_pred_PE.plg441.00 B22-02-09|14:06
run_decoding.v11.61 kB30-04-08|11:58
sum.v23.78 kB30-04-08|11:58
syntax_decoding.v24.94 kB30-04-08|11:58
timescale.v546.00 B30-04-08|11:58
total_zeros_decoding.v14.96 kB30-04-08|11:58
vsim.wlf32.00 kB24-02-09|16:06
_primary.dat73.20 kB24-02-09|15:26
_primary.vhd11.00 kB24-02-09|15:26
verilog.asm49.59 kB21-02-09|17:50
_primary.dat7.28 kB21-02-09|17:50
_primary.vhd1.23 kB21-02-09|17:50
verilog.asm275.78 kB24-02-09|15:27
_primary.dat39.36 kB24-02-09|15:27
_primary.vhd4.99 kB24-02-09|15:27
_primary.dat15.08 kB26-02-09|11:49
_primary.vhd3.73 kB26-02-09|11:49
_primary.dat17.38 kB26-02-09|11:49
_primary.vhd4.65 kB26-02-09|11:49
verilog.asm61.01 kB22-02-09|21:56
_primary.dat8.81 kB19-02-09|20:59
_primary.vhd3.04 kB22-02-09|21:56
verilog.asm15.53 kB24-02-09|15:27
_primary.dat1.24 kB24-02-09|15:27
_primary.vhd902.00 B24-02-09|15:27
_primary.dat986.00 B26-02-09|11:49
_primary.vhd419.00 B26-02-09|11:49
_primary.dat1.40 kB26-02-09|11:49
_primary.vhd749.00 B26-02-09|11:49
_primary.dat328.00 B26-02-09|11:49
_primary.vhd307.00 B26-02-09|11:49
_primary.dat687.00 B26-02-09|11:49
_primary.vhd291.00 B26-02-09|11:49
_primary.dat1.73 kB26-02-09|11:24
_primary.vhd585.00 B26-02-09|11:24
_info2.66 kB26-02-09|11:49
syntmp0.00 B22-02-09|14:46
@inter_pred_reg_ctrl0.00 B24-02-09|15:26
@intra4x4_@pred@mode_decoding0.00 B21-02-09|17:50
@intra_pred_@p@e0.00 B24-02-09|15:27
@intra_pred_pipeline0.00 B26-02-09|11:49
@intra_pred_reg_ctrl0.00 B26-02-09|11:49
@intra_pred_top0.00 B22-02-09|21:56
@p@e0.00 B24-02-09|15:27
main_seed_precomputation0.00 B26-02-09|11:49
plane_@h@v_precomputation0.00 B26-02-09|11:49
plane_a_precomputation0.00 B26-02-09|11:49
plane_bc_precomputation0.00 B26-02-09|11:49
ram_sync_1r_sync_1w0.00 B26-02-09|11:24
_temp0.00 B26-02-09|11:49
rev_10.00 B22-02-09|14:06
work0.00 B26-02-09|11:49
H.2640.00 B08-03-09|19:18
...
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