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nova_defines.v ( File view )

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  • By culourwq 2016-05-23
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			//--------------------------------------------------------------------------------------------------
// Design    : nova
// Author(s) : Ke Xu
// Email	   : eexuke@yahoo.com
// File      : nova_defines.v
// Generated : April 20,2008
// Copyright (C) 2008 Ke Xu                
//-------------------------------------------------------------------------------------------------
// Description 
// Global parameters of nova
//-------------------------------------------------------------------------------------------------

//-------------------------------------------------------------------------------------------------
//BitStream_controller parameters
//-------------------------------------------------------------------------------------------------

//---Beha_BitStream_ram.v---
`define Beha_Bitstream_ram_size	131071  //Beha_Bitstream_ram size

//bitstream_gclk_gen
//Assume running at 1.5MHz,so 50,000 cycles is needed for each frame
//1)50,000 cycles are not enough for foreman300,8th   frame.So increase to 51,000 cycles
//2)51,000 cycles are not enough for foreman300,11th  frame.So increase to 51,500 cycles
//3)51,500 cycles are not enough for foreman300,38th  frame.So increase to 52,000 cycles
//4)52,000 cycles are not enough for foreman300,66th  frame.So increase to 52,500 cycles
//5)52,500 cycles are not enough for foreman300,138th frame.So increase to 55,000 cycles
//6)55,000 cycles are not enough for foreman300,223th frame.So increase to 56,000 cycles
//After ext_frame_RAM is changed from async read (the FPGA does not support async read mode)to sync read,
//the cycles required to decode each frame increased
//7)56,000 cycles are not enough for foreman300,138th frame.So increase to 56,500 cycles
//8)56,500 cycles are not enough for foreman300,223th frame.So increase to 57,300 cycles
`define cycles_per_frame0 17'd45000
`define cycles_per_frame1 17'd50000 //fast enough for akiyo300
`define cycles_per_frame2	17'd57300 //preferred frequency for most critical sequence:foreman300
`define cycles_per_frame3	17'd70000

//---pc_decoding---
`define rst_consumed_bits_sel 3'b000
`define exp_golomb            3'b001
`define fixed_length          3'b011
`define dependent_variable    3'b010
`define cavlc_consumed        3'b110
`define trailing_bits         3'b111
`define pcm_alignment         3'b101

//---syntax_decoding---
//mb_type_general
`define MB_Inter16x16            4'b0000
`define MB_Inter16x8             4'b0001
`define MB_Inter8x16             4'b0010
`define MB_P_8x8                 4'b0011
`define MB_P_8x8ref0             4'b0100	
`define MB_P_skip                4'b0101
`define MB_I_PCM                 4'b0110		
`define MB_type_reserved0        4'b0111
`define MB_Intra16x16_CBPChroma0 4'b1000
`define MB_Intra16x16_CBPChroma1 4'b1001
`define MB_Intra16x16_CBPChroma2 4'b1010
`define MB_type_reserved1        4'b1011
`define MB_Intra4x4              4'b1100
`define MB_type_reserved2        4'b1101
`define MB_type_reserved3        4'b1110
`define MB_type_rst              4'b1111

//MBTypeGen_mbAddrA,MBTypeGen_mbAddrB_reg
`define MB_addrA_addrB_Inter      2'b00
`define MB_addrA_addrB_P_skip     2'b01
`define MB_addrA_addrB_Intra16x16 2'b10
`define MB_addrA_addrB_Intra4x4   2'b11

//MBTypeGen_mbAddrD
`define MB_addrD_Inter_P_skip 1'b0
`define MB_addrD_Intra        1'b1

//Gray-encoded FSM states to reduce power consumption during state switching
`define rst_parser 		    2'b00
`define start_code_prefix 2'b01
`define nal_unit 			    2'b11

`define rst_nal_unit						           3'b000
`define forbidden_zero_bit_2_nal_unit_type 3'b001
`define slice_layer_non_IDR_rbsp			     3'b011
`define slice_layer_IDR_rbsp				       3'b010
`define seq_parameter_set_rbsp			       3'b110
`define pic_parameter_set_rbsp		  	     3'b111
`define rbsp_trailing_one_bit				       3'b101
`define rbsp_trailing_zero_bits		         3'b100

`define rst_slice_layer_wo_partitioning 2'b00
`define slice_header				            2'b01
`define slice_data				              2'b11

`define rst_seq_parameter_set                     4'b0000
`define fixed_header                              4'b0001
`define level_idc_s                               4'b0011
`define seq_parameter_set_id_sps_s                4'b0010
`define log2_max_frame_num_minus4_s               4'b0110
`define pic_order_cnt_type_s                      4'b0111
`define log2_max_pic_order_cnt_lsb_minus4_s       4'b0101
`define num_ref_frames_s                          4'b0100
`define gaps_in_frame_num_value_allowed_flag_s    4'b1100
`define pic_width_in_mbs_minus1_s                 4'b1101
`define pic_height_in_map_units_minus1_s          4'b1111
`define frame_mbs_only_flag_2_frame_cropping_flag 4'b1110
`define vui_parameter_present_flag_s              4'b1010

`define rst_pic_parameter_set								 		                   4'b0000
`define pic_parameter_set_id_pps_s								                 4'b0001
`define seq_parameter_set_id_pps_s								                 4'b0011
`define entropy_coding_mode_flag_2_pic_order_present_flag			     4'b0010
`define num_slice_groups_minus1_s									                 4'b0110
`define num_ref_idx_l0_active_minus1_pps_s						             4'b0111
`define num_ref_idx_l1_active_minus1_pps_s						             4'b0101
`define weighted_pred_flag_2_weighted_bipred_idc					         4'b0100
`define pic_init_qp_minus26_s										                   4'b1100
`define pic_init_qs_minus26_s										                   4'b1101
`define chroma_qp_index_offset_s									                 4'b1111
`define deblocking_filter_control_2_redundant_pic_cnt_present_flag 4'b1110

`define rst_slice_header							              4'b0000
`define first_mb_in_slice_s						              4'b0001
`define slice_type_s								                4'b0011
`define pic_parameter_set_id_slice_header_s		      4'b0010
`define frame_num_s								                  4'b0110
`define idr_pic_id_s								                4'b0111
`define pic_order_cnt_lsb_s						              4'b0101
`define num_ref_idx_active_override_flag_s		      4'b0100
`define num_ref_idx_l0_active_minus1_slice_header_s 4'b1100
`define ref_pic_list_reordering					            4'b1101
`define dec_ref_pic_marking						              4'b1111
`define slice_qp_delta_s							              4'b1110
`define disable_deblocking_filter_idc_s			        4'b1010
`define slice_alpha_c0_offset_div2_s				        4'b1011
`define slice_beta_offset_div2_s					          4'b1001

//ref_pic_list_reordering_state 
`define rst_ref_pic_list_reordering		    3'b000
`define ref_pic_list_reordering_flag_l0_s 3'b001

//dec_ref_pic_marking_state 
`define rst_dec_ref_pic_marking								                  2'b00
`define no_output_of_prior_pics_flag_2_long_term_reference_flag 2'b01
`define adaptive_ref_pic_marking_mode_flag_s					          2'b11

`define rst_slice_data		       4'b0000
`define mb_skip_run_s			       4'b0001
`define skip_run_duration		     4'b0011
`define mb_type_s				         4'b0010
`define pcm_alignment_zero_bit_s 4'b0110
`define pcm_byte_s			         4'b0111
`define sub_mb_pred			         4'b0101
`define mb_pred				           4'b0100
`define coded_block_pattern_s	   4'b1100
`define mb_qp_delta_s			       4'b1101
`define residual				         4'b1111
`define mb_num_update			       4'b1110

//mb_pred_state 
`define rst_mb_pred					           3'b000
`define prev_intra4x4_pred_mode_flag_s 3'b001
`define rem_intra4x4_pred_mode_s	     3'b011
`define intra_chroma_pred_mode_s	     3'b010
`define ref_idx_l0_s				           3'b110
`define mvd_l0_s					             3'b111

//sub_mb_pred_state 
`define rst_sub_mb_pred  2'b00
`define sub_mb_type_s	   2'b01
`define sub_ref_idx_l0_s 2'b11
`define sub_mvd_l0_s	   2'b10

`define rst_residual		      4'b0000
`define Intra16x16DCLevel_s	  4'b0001
`define Intra16x16ACLevel_s	  4'b0011
`define Intra16x16ACLevel_0_s 4'b0010
`define LumaLevel_s			      4'b0110
`define LumaLevel_0_s		      4'b0111
`define ChromaDCLevel_Cb_s    4'b0101
`define ChromaDCLevel_Cr_s	  4'b0100
`define ChromaACLevel_Cb_s	  4'b1100
`define ChromaACLevel_Cr_s	  4'b1101
`define ChromaACLevel_0_s		  4'b1110

`define rst_cavlc_decoder		     4'b0000
`define nAnB_decoding_s		       4'b0001	
`define nC_decoding_s			       4'b0011
`define NumCoeffTrailingOnes_LUT 4'b0010
`define TrailingOnesSignFlag
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Name Size Date
Beha_BitStream_ram.v1.16 kB30-04-08|11:58
BitStream_buffer.v11.65 kB30-04-08|11:58
BitStream_controller.v25.60 kB30-04-08|11:58
bitstream_gclk_gen.v12.67 kB30-04-08|11:58
BitStream_parser_FSM_gating.v27.58 kB30-04-08|11:58
bs_decoding.v45.34 kB30-04-08|11:58
cavlc_consumed_bits_decoding.v1.85 kB30-04-08|11:58
cavlc_decoder.v10.33 kB30-04-08|11:58
CodedBlockPattern_decoding.v5.83 kB30-04-08|11:58
dependent_variable_decoding.v2.42 kB30-04-08|11:58
DF_mem_ctrl.v29.69 kB30-04-08|11:58
DF_pipeline.v33.65 kB30-04-08|11:58
DF_reg_ctrl.v15.94 kB30-04-08|11:58
DF_top.v7.41 kB30-04-08|11:58
end_of_blk_decoding.v2.82 kB30-04-08|11:58
exp_golomb_decoding.v6.17 kB30-04-08|11:58
ext_frame_RAM0_wrapper.v5.09 kB30-04-08|11:58
ext_frame_RAM1_wrapper.v5.10 kB30-04-08|11:58
ext_RAM_ctrl.v3.46 kB30-04-08|11:58
H.264.cr.mti2.20 kB28-02-09|13:54
H.264.mpf55.79 kB28-02-09|00:05
heading_one_detector.v2.51 kB30-04-08|11:58
hybrid_pipeline_ctrl.v10.79 kB30-04-08|11:58
Inter_mv_decoding.v93.25 kB30-04-08|11:58
Inter_pred_CPE.v3.74 kB30-04-08|11:58
Inter_pred_LPE.v23.87 kB30-04-08|11:58
Inter_pred_pipeline.v33.29 kB30-04-08|11:58
Inter_pred_reg_ctrl.v124.27 kB30-04-08|11:58
Inter_pred_sliding_window.v130.18 kB30-04-08|11:58
Inter_pred_top.v28.66 kB30-04-08|11:58
Intra4x4_PredMode_decoding.v14.99 kB30-04-08|11:58
Intra_pred_PE.v69.16 kB30-04-08|11:58
Intra_pred_pipeline.v32.46 kB24-02-09|22:46
Intra_pred_reg_ctrl.v36.37 kB30-04-08|11:58
Intra_pred_top.v14.40 kB30-04-08|11:58
IQIT.v32.48 kB30-04-08|11:58
level_decoding.v7.45 kB30-04-08|11:58
nC_decoding.v30.47 kB30-04-08|11:58
nova.v8.19 kB30-04-08|11:58
nova_defines.v12.10 kB30-04-08|11:58
nova_tb.v2.92 kB30-04-08|11:58
NumCoeffTrailingOnes_decoding.v25.79 kB30-04-08|11:58
pc_decoding.v10.34 kB30-04-08|11:58
QP_decoding.v2.31 kB30-04-08|11:58
ram_async_1r_sync_1w.v2.71 kB30-04-08|11:58
ram_sync_1r_sync_1w.v3.01 kB30-04-08|11:58
reconstruction.v22.49 kB30-04-08|11:58
rec_DF_RAM0_96x32.v18.23 kB30-04-08|11:58
rec_DF_RAM0_wrapper.v1.73 kB30-04-08|11:58
rec_DF_RAM1_96x32.v18.23 kB30-04-08|11:58
rec_DF_RAM1_wrapper.v1.73 kB30-04-08|11:58
rec_DF_RAM_ctrl.v6.42 kB30-04-08|11:58
rec_gclk_gen.v16.68 kB30-04-08|11:58
Intra_pred_PE.areasrr10.14 kB22-02-09|14:06
Intra_pred_PE.edn2.76 MB22-02-09|14:06
Intra_pred_PE.fse0.00 B22-02-09|14:06
Intra_pred_PE.sdf2.05 MB22-02-09|14:06
Intra_pred_PE.srd1.03 MB22-02-09|14:06
Intra_pred_PE.srm1.61 MB22-02-09|14:06
Intra_pred_PE.srr34.82 kB22-02-09|14:06
Intra_pred_PE.srs102.69 kB22-02-09|14:06
Intra_pred_PE.tlg418.00 B22-02-09|14:06
Intra_pred_PE_sdc.sdc310.00 B22-02-09|14:06
Intra_pred_PE.msg0.00 B22-02-09|14:46
Intra_pred_PE.plg441.00 B22-02-09|14:06
run_decoding.v11.61 kB30-04-08|11:58
sum.v23.78 kB30-04-08|11:58
syntax_decoding.v24.94 kB30-04-08|11:58
timescale.v546.00 B30-04-08|11:58
total_zeros_decoding.v14.96 kB30-04-08|11:58
vsim.wlf32.00 kB24-02-09|16:06
_primary.dat73.20 kB24-02-09|15:26
_primary.vhd11.00 kB24-02-09|15:26
verilog.asm49.59 kB21-02-09|17:50
_primary.dat7.28 kB21-02-09|17:50
_primary.vhd1.23 kB21-02-09|17:50
verilog.asm275.78 kB24-02-09|15:27
_primary.dat39.36 kB24-02-09|15:27
_primary.vhd4.99 kB24-02-09|15:27
_primary.dat15.08 kB26-02-09|11:49
_primary.vhd3.73 kB26-02-09|11:49
_primary.dat17.38 kB26-02-09|11:49
_primary.vhd4.65 kB26-02-09|11:49
verilog.asm61.01 kB22-02-09|21:56
_primary.dat8.81 kB19-02-09|20:59
_primary.vhd3.04 kB22-02-09|21:56
verilog.asm15.53 kB24-02-09|15:27
_primary.dat1.24 kB24-02-09|15:27
_primary.vhd902.00 B24-02-09|15:27
_primary.dat986.00 B26-02-09|11:49
_primary.vhd419.00 B26-02-09|11:49
_primary.dat1.40 kB26-02-09|11:49
_primary.vhd749.00 B26-02-09|11:49
_primary.dat328.00 B26-02-09|11:49
_primary.vhd307.00 B26-02-09|11:49
_primary.dat687.00 B26-02-09|11:49
_primary.vhd291.00 B26-02-09|11:49
_primary.dat1.73 kB26-02-09|11:24
_primary.vhd585.00 B26-02-09|11:24
_info2.66 kB26-02-09|11:49
syntmp0.00 B22-02-09|14:46
@inter_pred_reg_ctrl0.00 B24-02-09|15:26
@intra4x4_@pred@mode_decoding0.00 B21-02-09|17:50
@intra_pred_@p@e0.00 B24-02-09|15:27
@intra_pred_pipeline0.00 B26-02-09|11:49
@intra_pred_reg_ctrl0.00 B26-02-09|11:49
@intra_pred_top0.00 B22-02-09|21:56
@p@e0.00 B24-02-09|15:27
main_seed_precomputation0.00 B26-02-09|11:49
plane_@h@v_precomputation0.00 B26-02-09|11:49
plane_a_precomputation0.00 B26-02-09|11:49
plane_bc_precomputation0.00 B26-02-09|11:49
ram_sync_1r_sync_1w0.00 B26-02-09|11:24
_temp0.00 B26-02-09|11:49
rev_10.00 B22-02-09|14:06
work0.00 B26-02-09|11:49
H.2640.00 B08-03-09|19:18
...
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