Home » Source Code » H264 Verilog » Intra_pred_top.v

Intra_pred_top.v ( File view )

From:H264 Verilog
  • By culourwq 2016-05-23
  • View(s):0
  • Download(s):2
  • Point(s): 1
			//--------------------------------------------------------------------------------------------------
// Design    : nova
// Author(s) : Ke Xu
// Email	   : eexuke@yahoo.com
// File      : Intra_pred_top.v
// Generated : Sep 30,2005
// Copyright (C) 2008 Ke Xu                
//-------------------------------------------------------------------------------------------------
// Description 
// Top module of Intra prediction
//-------------------------------------------------------------------------------------------------

// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "nova_defines.v"

module Intra_pred_top (clk,reset_n,
	gclk_intra_mbAddrA_luma,gclk_intra_mbAddrA_Cb,gclk_intra_mbAddrA_Cr,gclk_intra_mbAddrB,
	gclk_intra_mbAddrC_luma,gclk_intra_mbAddrD,gclk_seed,gclk_Intra_mbAddrB_RAM,
	mb_num_h,mb_num_v,mb_type_general,NextMB_IsSkip,
	Intra16x16_predmode,Intra4x4_predmode_CurrMb,Intra_chroma_predmode,
	blk4x4_rec_counter,trigger_blk4x4_intra_pred,blk4x4_sum_counter,
	sum_right_column_reg,blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out,
	blk4x4_pred_output0, blk4x4_pred_output1, blk4x4_pred_output2,
	blk4x4_pred_output4, blk4x4_pred_output5, blk4x4_pred_output6,
	blk4x4_pred_output8, blk4x4_pred_output9, blk4x4_pred_output10,
	blk4x4_pred_output12,blk4x4_pred_output13,blk4x4_pred_output14,
	Intra_mbAddrB_RAM_wr,Intra_mbAddrB_RAM_wr_addr,Intra_mbAddrB_RAM_din,
	
	PE0_out,PE1_out,PE2_out,PE3_out,Intra4x4_predmode,
	blk4x4_intra_preload_counter,blk4x4_intra_precompute_counter,blk4x4_intra_calculate_counter,
	end_of_one_blk4x4_intra,Intra_mbAddrB_RAM_rd
	);
	input clk,reset_n;
	input gclk_intra_mbAddrA_luma;
	input gclk_intra_mbAddrA_Cb;
	input gclk_intra_mbAddrA_Cr;
	input gclk_intra_mbAddrB; 
	input gclk_intra_mbAddrC_luma;	
	input gclk_intra_mbAddrD;
	input gclk_seed;
	input gclk_Intra_mbAddrB_RAM;
	input [3:0] mb_num_h;
	input [3:0] mb_num_v;
	input [3:0] mb_type_general;
	input NextMB_IsSkip;
	input [1:0] Intra16x16_predmode;
	input [63:0] Intra4x4_predmode_CurrMb;
	input [1:0] Intra_chroma_predmode;
	input [4:0] blk4x4_rec_counter;
	input trigger_blk4x4_intra_pred;
	input [2:0] blk4x4_sum_counter;
	input [23:0] sum_right_column_reg;
	input [7:0] blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out;
	input [7:0] blk4x4_pred_output0, blk4x4_pred_output1, blk4x4_pred_output2;
	input [7:0] blk4x4_pred_output4, blk4x4_pred_output5, blk4x4_pred_output6;
	input [7:0] blk4x4_pred_output8, blk4x4_pred_output9, blk4x4_pred_output10;
	input [7:0] blk4x4_pred_output12,blk4x4_pred_output13,blk4x4_pred_output14;
	input Intra_mbAddrB_RAM_wr;
	input [6:0] Intra_mbAddrB_RAM_wr_addr;
	input [31:0] Intra_mbAddrB_RAM_din;
	
	output [7:0] PE0_out;
	output [7:0] PE1_out;
	output [7:0] PE2_out;
	output [7:0] PE3_out;
	output [3:0] Intra4x4_predmode;
	output [2:0] blk4x4_intra_preload_counter;
	output [3:0] blk4x4_intra_precompute_counter;
	output [2:0] blk4x4_intra_calculate_counter;
	output end_of_one_blk4x4_intra;
	output Intra_mbAddrB_RAM_rd;
		
	wire blkAddrA_availability,blkAddrB_availability;
	wire mbAddrA_availability,mbAddrB_availability,mbAddrC_availability;
	wire [7:0] blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out;
	wire [15:0] PE0_sum_out,PE3_sum_out;
	wire Intra_mbAddrB_RAM_rd;
	wire [6:0] Intra_mbAddrB_RAM_rd_addr;
	wire [31:0]	Intra_mbAddrB_RAM_dout;
	
	wire [7:0] Intra_mbAddrA_window0,Intra_mbAddrA_window1,Intra_mbAddrA_window2,Intra_mbAddrA_window3;
	wire [7:0] Intra_mbAddrA_reg0, Intra_mbAddrA_reg1, Intra_mbAddrA_reg2, Intra_mbAddrA_reg3;
	wire [7:0] Intra_mbAddrA_reg4, Intra_mbAddrA_reg5, Intra_mbAddrA_reg6, Intra_mbAddrA_reg7;
	wire [7:0] Intra_mbAddrA_reg8, Intra_mbAddrA_reg9, Intra_mbAddrA_reg10,Intra_mbAddrA_reg11;
	wire [7:0] Intra_mbAddrA_reg12,Intra_mbAddrA_reg13,Intra_mbAddrA_reg14,Intra_mbAddrA_reg15;
	
	wire [7:0] Intra_mbAddrB_window0,Intra_mbAddrB_window1,Intra_mbAddrB_window2,Intra_mbAddrB_window3;
	wire [7:0] Intra_mbAddrB_reg0, Intra_mbAddrB_reg1, Intra_mbAddrB_reg2, Intra_mbAddrB_reg3;
	wire [7:0] Intra_mbAddrB_reg4, Intra_mbAddrB_reg5, Intra_mbAddrB_reg6, Intra_mbAddrB_reg7;
	wire [7:0] Intra_mbAddrB_reg8, Intra_mbAddrB_reg9, Intra_mbAddrB_reg10,Intra_mbAddrB_reg11;
	wire [7:0] Intra_mbAddrB_reg12,Intra_mbAddrB_reg13,Intra_mbAddrB_reg14,Intra_mbAddrB_reg15;
	
	wire [7:0] Intra_mbAddrC_window0,Intra_mbAddrC_window1,Intra_mbAddrC_window2,Intra_mbAddrC_window3; 
	wire [7:0] Intra_mbAddrD_window;
	wire [15:0] main_seed,seed;
	wire [11:0] plane_b_reg,plane_c_reg;
	
	Intra_pred_pipeline Intra_pred_pipeline (
		.clk(clk),
		.reset_n(reset_n),
		.mb_type_general(mb_type_general),
		.blk4x4_rec_counter(blk4x4_rec_counter),
		.trigger_blk4x4_intra_pred(trigger_blk4x4_intra_pred),
		.mb_num_v(mb_num_v),
		.mb_num_h(mb_num_h),
		.blk4x4_sum_counter(blk4x4_sum_counter),
		.NextMB_IsSkip(NextMB_IsSkip),
		.Intra16x16_predmode(Intra16x16_predmode),
		.Intra4x4_predmode_CurrMb(Intra4x4_predmode_CurrMb),
		.Intra_chroma_predmode(Intra_chroma_predmode),
		.Intra_mbAddrA_reg0(Intra_mbAddrA_reg0), 
		.Intra_mbAddrA_reg1(Intra_mbAddrA_reg1), 
		.Intra_mbAddrA_reg2(Intra_mbAddrA_reg2), 
		.Intra_mbAddrA_reg3(Intra_mbAddrA_reg3),
		.Intra_mbAddrA_reg4(Intra_mbAddrA_reg4), 
		.Intra_mbAddrA_reg5(Intra_mbAddrA_reg5), 
		.Intra_mbAddrA_reg6(Intra_mbAddrA_reg6), 
		.Intra_mbAddrA_reg7(Intra_mbAddrA_reg7),
		.Intra_mbAddrA_reg8(Intra_mbAddrA_reg8), 
		.Intra_mbAddrA_reg9(Intra_mbAddrA_reg9), 
		.Intra_mbAddrA_reg10(Intra_mbAddrA_reg10),
		.Intra_mbAddrA_reg11(Intra_mbAddrA_reg11),
		.Intra_mbAddrA_reg12(Intra_mbAddrA_reg12),
		.Intra_mbAddrA_reg13(Intra_mbAddrA_reg13),
		.Intra_mbAddrA_reg14(Intra_mbAddrA_reg14),
		.Intra_mbAddrA_reg15(Intra_mbAddrA_reg15),
		.Intra_mbAddrB_reg0(Intra_mbAddrB_reg0), 
		.Intra_mbAddrB_reg1(Intra_mbAddrB_reg1), 
		.Intra_mbAddrB_reg2(Intra_mbAddrB_reg2), 
		.Intra_mbAddrB_reg3(Intra_mbAddrB_reg3),
		.Intra_mbAddrB_reg4(Intra_mbAddrB_reg4), 
		.Intra_mbAddrB_reg5(Intra_mbAddrB_reg5), 
		.Intra_mbAddrB_reg6(Intra_mbAddrB_reg6), 
		.Intra_mbAddrB_reg7(Intra_mbAddrB_reg7),
		.Intra_mbAddrB_reg8(Intra_mbAddrB_reg8), 
		.Intra_mbAddrB_reg9(Intra_mbAddrB_reg9), 
		.Intra_mbAddrB_reg10(Intra_mbAddrB_reg10),
		.Intra_mbAddrB_reg11(Intra_mbAddrB_reg11),
		.Intra_mbAddrB_reg12(Intra_mbAddrB_reg12),
		.Intra_mbAddrB_reg13(Intra_mbAddrB_reg13),
		.Intra_mbAddrB_reg14(Intra_mbAddrB_reg14),
		.Intra_mbAddrB_reg15(Intra_mbAddrB_reg15),
		.Intra_mbAddrD_window(Intra_mbAddrD_window),
		
		.Intra4x4_predmode(Intra4x4_predmode),
		.blk4x4_intra_preload_counter(blk4x4_intra_preload_counter),
		.blk4x4_intra_precompute_counter(blk4x4_intra_precompute_counter),
		.blk4x4_intra_calculate_counter(blk4x4_intra_calculate_counter),
		.end_of_one_blk4x4_intra(end_of_one_blk4x4_intra),
		.blkAddrA_availability(blkAddrA_availability),
		.blkAddrB_availability(blkAddrB_availability),
		.mbAddrA_availability(mbAddrA_availability),
		.mbAddrB_availability(mbAddrB_availability),
		.mbAddrC_availability(mbAddrC_availability),
		.main_seed(main_seed),
		.plane_b_reg(plane_b_reg),
		.plane_c_reg(plane_c_reg),
		.Intra_mbAddrB_RAM_rd(Intra_mbAddrB_RAM_rd),
		.Intra_mbAddrB_RAM_rd_addr(Intra_mbAddrB_RAM_rd_addr)
		);
		
	Intra_pred_reg_ctrl Intra_pred_reg_ctrl (
		.reset_n(reset_n),
		.gclk_intra_mbAddrA_luma(gclk_intra_mbAddrA_luma),
	 	.gclk_intra_mbAddrA_Cb(gclk_intra_mbAddrA_Cb),
	 	.gclk_intra_mbAddrA_Cr(gclk_intra_mbAddrA_Cr),
	 	.gclk_intra_mbAddrB(gclk_intra_mbAddrB), 
	 	.gclk_intra_mbAddrC_luma(gclk_intra_mbAddrC_luma),	
	 	.gclk_intra_mbAddrD(gclk_intra_mbAddrD),
	 	.gclk_seed(gclk_seed),
		.mbAddrA_availability(mbAddrA_availability),
		.mbAddrC_availability(mbAddrC_availability),
		.blk4x4_rec_counter(blk4x4_rec_counter),
		.blk4x4_sum_counter(blk4x4_sum_counter),
		.blk4x4_intra_preload_counter(blk4x4_intra_preload_counter),
		.blk4x4_intra_precompute_counter(blk4x4_intra_precompute_counter),
		.blk4x4_intra_calculate_counter(blk4x4_intra_calculate_counter),
		.mb_type_general(mb_type_general),
		.Intra4x4_predmode(Intra4x4_predmode),
		.Intra16x16_predmode(Intra16x16_predmode),
		.Intra_chroma_predmode(Intra_chroma_predmode),
		.Intra_mbAddrB_RAM_dout(Intra_mbAddrB_RAM_dout),
		.sum_right_column_reg(sum_right_column_reg),
		.blk4x4_sum_PE0_out(blk4x4_sum_PE0_out),
		.blk4x4_sum_PE1_out(blk4x4_sum_PE1_out),
		.blk4x4_sum_PE2_out(blk4x4_sum_PE2_out),
		.blk4x4_sum_PE3_out(blk4x4_sum_PE3_out),
		.main_seed(main_seed),
		.PE0_sum_out(PE0_sum_out),
		.PE3_sum_out(PE3_sum_out),
		
		.Intra_mbAddrA_window0(Intra_mbAddrA_window0),
		.Intra_mbAddrA_window1(Intra_mbAddrA_window1),
		.Intra_mbAddrA_window2(Intra_mbAddrA_window2),
		.Intra_mbAddrA_window3(Intra_mbAddrA_window3),
		.Intra_mbAddrA_reg0(Intra_mbAddrA_reg0), 
		.Intra_mbAddrA_reg1(Intra_mbAddrA_reg1), 
		.Intra_mbAddrA_reg2(Intra_mbAddrA_reg2), 
		.Intra_mbAddrA_reg3(Intra_mbAddrA_reg3),
		.Intra_mbAddrA_reg4(Intra_mbAddrA_reg4), 
		.Intra_mbAddrA_reg5(Intra_mbAddrA_reg5), 
		.Intra_mbAddrA_reg6(Intra_mbAddrA_reg6), 
		.Intra_mbAddrA_reg7(Intra_mbAddrA_reg7),
		.Intra_mbAddrA_reg8(Intra_mbAddrA_reg8), 
		.Intra_mbAddrA_reg9(Intra_mbAddrA_reg9), 
		.Intra_mbAddrA_reg10(Intra_mbAddrA_reg10),
		.Intra_mbAddrA_reg11(Intra_mbAddrA_reg11),
		.Intra_mbAddrA_reg12(Intra_mbAddrA_reg12),
		.Intra_mbAddrA_reg13(Intra_mbAddrA_reg13),
		.Intra_mbAddrA_reg14(Intra_mbAddrA_reg14),
		.Intra_mbAddrA_reg15(Intra_mbAddrA_reg15),
		.Intra_mbAddrB_window0(Intra_mbAddrB_window0),
		.Intra_mbAddrB_window1(Intra_mbAddrB_window1),
		.Intra_mbAddrB_window2(Intra_mbAddrB_window2),
		.Intra_mbAddrB_window3(Intra_mbAddrB_window3),
		.Intra_mbAddrB_reg0(Intra_mbAddrB_reg0), 
		.Intra_mbAddrB_reg1(Intra_mbAddrB_reg1), 
		.Intra_mbAddrB_reg2(Intra_mbAddrB_reg2), 
		.Intra_mbAddrB_reg3(Intra_mbAddrB_reg3),
		.Intra_mbAddr
...
...
(Please download the complete source code to view)
			
...
Expand> <Close

Want complete source code? Download it here

Point(s): 1

Download
0 lines left, continue to read
Sponsored links

File list

Tips: You can preview the content of files by clicking file names^_^
Name Size Date
Beha_BitStream_ram.v1.16 kB30-04-08|11:58
BitStream_buffer.v11.65 kB30-04-08|11:58
BitStream_controller.v25.60 kB30-04-08|11:58
bitstream_gclk_gen.v12.67 kB30-04-08|11:58
BitStream_parser_FSM_gating.v27.58 kB30-04-08|11:58
bs_decoding.v45.34 kB30-04-08|11:58
cavlc_consumed_bits_decoding.v1.85 kB30-04-08|11:58
cavlc_decoder.v10.33 kB30-04-08|11:58
CodedBlockPattern_decoding.v5.83 kB30-04-08|11:58
dependent_variable_decoding.v2.42 kB30-04-08|11:58
DF_mem_ctrl.v29.69 kB30-04-08|11:58
DF_pipeline.v33.65 kB30-04-08|11:58
DF_reg_ctrl.v15.94 kB30-04-08|11:58
DF_top.v7.41 kB30-04-08|11:58
end_of_blk_decoding.v2.82 kB30-04-08|11:58
exp_golomb_decoding.v6.17 kB30-04-08|11:58
ext_frame_RAM0_wrapper.v5.09 kB30-04-08|11:58
ext_frame_RAM1_wrapper.v5.10 kB30-04-08|11:58
ext_RAM_ctrl.v3.46 kB30-04-08|11:58
H.264.cr.mti2.20 kB28-02-09|13:54
H.264.mpf55.79 kB28-02-09|00:05
heading_one_detector.v2.51 kB30-04-08|11:58
hybrid_pipeline_ctrl.v10.79 kB30-04-08|11:58
Inter_mv_decoding.v93.25 kB30-04-08|11:58
Inter_pred_CPE.v3.74 kB30-04-08|11:58
Inter_pred_LPE.v23.87 kB30-04-08|11:58
Inter_pred_pipeline.v33.29 kB30-04-08|11:58
Inter_pred_reg_ctrl.v124.27 kB30-04-08|11:58
Inter_pred_sliding_window.v130.18 kB30-04-08|11:58
Inter_pred_top.v28.66 kB30-04-08|11:58
Intra4x4_PredMode_decoding.v14.99 kB30-04-08|11:58
Intra_pred_PE.v69.16 kB30-04-08|11:58
Intra_pred_pipeline.v32.46 kB24-02-09|22:46
Intra_pred_reg_ctrl.v36.37 kB30-04-08|11:58
Intra_pred_top.v14.40 kB30-04-08|11:58
IQIT.v32.48 kB30-04-08|11:58
level_decoding.v7.45 kB30-04-08|11:58
nC_decoding.v30.47 kB30-04-08|11:58
nova.v8.19 kB30-04-08|11:58
nova_defines.v12.10 kB30-04-08|11:58
nova_tb.v2.92 kB30-04-08|11:58
NumCoeffTrailingOnes_decoding.v25.79 kB30-04-08|11:58
pc_decoding.v10.34 kB30-04-08|11:58
QP_decoding.v2.31 kB30-04-08|11:58
ram_async_1r_sync_1w.v2.71 kB30-04-08|11:58
ram_sync_1r_sync_1w.v3.01 kB30-04-08|11:58
reconstruction.v22.49 kB30-04-08|11:58
rec_DF_RAM0_96x32.v18.23 kB30-04-08|11:58
rec_DF_RAM0_wrapper.v1.73 kB30-04-08|11:58
rec_DF_RAM1_96x32.v18.23 kB30-04-08|11:58
rec_DF_RAM1_wrapper.v1.73 kB30-04-08|11:58
rec_DF_RAM_ctrl.v6.42 kB30-04-08|11:58
rec_gclk_gen.v16.68 kB30-04-08|11:58
Intra_pred_PE.areasrr10.14 kB22-02-09|14:06
Intra_pred_PE.edn2.76 MB22-02-09|14:06
Intra_pred_PE.fse0.00 B22-02-09|14:06
Intra_pred_PE.sdf2.05 MB22-02-09|14:06
Intra_pred_PE.srd1.03 MB22-02-09|14:06
Intra_pred_PE.srm1.61 MB22-02-09|14:06
Intra_pred_PE.srr34.82 kB22-02-09|14:06
Intra_pred_PE.srs102.69 kB22-02-09|14:06
Intra_pred_PE.tlg418.00 B22-02-09|14:06
Intra_pred_PE_sdc.sdc310.00 B22-02-09|14:06
Intra_pred_PE.msg0.00 B22-02-09|14:46
Intra_pred_PE.plg441.00 B22-02-09|14:06
run_decoding.v11.61 kB30-04-08|11:58
sum.v23.78 kB30-04-08|11:58
syntax_decoding.v24.94 kB30-04-08|11:58
timescale.v546.00 B30-04-08|11:58
total_zeros_decoding.v14.96 kB30-04-08|11:58
vsim.wlf32.00 kB24-02-09|16:06
_primary.dat73.20 kB24-02-09|15:26
_primary.vhd11.00 kB24-02-09|15:26
verilog.asm49.59 kB21-02-09|17:50
_primary.dat7.28 kB21-02-09|17:50
_primary.vhd1.23 kB21-02-09|17:50
verilog.asm275.78 kB24-02-09|15:27
_primary.dat39.36 kB24-02-09|15:27
_primary.vhd4.99 kB24-02-09|15:27
_primary.dat15.08 kB26-02-09|11:49
_primary.vhd3.73 kB26-02-09|11:49
_primary.dat17.38 kB26-02-09|11:49
_primary.vhd4.65 kB26-02-09|11:49
verilog.asm61.01 kB22-02-09|21:56
_primary.dat8.81 kB19-02-09|20:59
_primary.vhd3.04 kB22-02-09|21:56
verilog.asm15.53 kB24-02-09|15:27
_primary.dat1.24 kB24-02-09|15:27
_primary.vhd902.00 B24-02-09|15:27
_primary.dat986.00 B26-02-09|11:49
_primary.vhd419.00 B26-02-09|11:49
_primary.dat1.40 kB26-02-09|11:49
_primary.vhd749.00 B26-02-09|11:49
_primary.dat328.00 B26-02-09|11:49
_primary.vhd307.00 B26-02-09|11:49
_primary.dat687.00 B26-02-09|11:49
_primary.vhd291.00 B26-02-09|11:49
_primary.dat1.73 kB26-02-09|11:24
_primary.vhd585.00 B26-02-09|11:24
_info2.66 kB26-02-09|11:49
syntmp0.00 B22-02-09|14:46
@inter_pred_reg_ctrl0.00 B24-02-09|15:26
@intra4x4_@pred@mode_decoding0.00 B21-02-09|17:50
@intra_pred_@p@e0.00 B24-02-09|15:27
@intra_pred_pipeline0.00 B26-02-09|11:49
@intra_pred_reg_ctrl0.00 B26-02-09|11:49
@intra_pred_top0.00 B22-02-09|21:56
@p@e0.00 B24-02-09|15:27
main_seed_precomputation0.00 B26-02-09|11:49
plane_@h@v_precomputation0.00 B26-02-09|11:49
plane_a_precomputation0.00 B26-02-09|11:49
plane_bc_precomputation0.00 B26-02-09|11:49
ram_sync_1r_sync_1w0.00 B26-02-09|11:24
_temp0.00 B26-02-09|11:49
rev_10.00 B22-02-09|14:06
work0.00 B26-02-09|11:49
H.2640.00 B08-03-09|19:18
...
Sponsored links

Intra_pred_top.v (808.37 kB)

Need 1 point
Your Point(s)

Your Point isn't enough.

Get point immediately by PayPal

More(Debit card / Credit card / PayPal Credit / Online Banking)

Submit your source codes. Get more point

LOGIN

Don't have an account? Register now
Need any help?
Mail to: support@codeforge.com

切换到中文版?

CodeForge Chinese Version
CodeForge English Version

Where are you going?

^_^"Oops ...

Sorry!This guy is mysterious, its blog hasn't been opened, try another, please!
OK

Warm tip!

CodeForge to FavoriteFavorite by Ctrl+D