Home » Source Code » H264 Verilog » Intra4x4_PredMode_decoding.v

Intra4x4_PredMode_decoding.v ( File view )

From:H264 Verilog
  • By culourwq 2016-05-23
  • View(s):0
  • Download(s):2
  • Point(s): 1
			//--------------------------------------------------------------------------------------------------
// Design    : nova
// Author(s) : Ke Xu
// Email	   : eexuke@yahoo.com
// File      : Intra4x4_PredMode_decoding.v
// Generated : May 31, 2005
// Copyright (C) 2008 Ke Xu                
//-------------------------------------------------------------------------------------------------
// Description 
// Decoding the prediction mode for Intra4x4	
//-------------------------------------------------------------------------------------------------

// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "nova_defines.v"

module Intra4x4_PredMode_decoding (clk,reset_n,mb_pred_state,luma4x4BlkIdx,mb_num_h,mb_num_v,
	MBTypeGen_mbAddrA,MBTypeGen_mbAddrB_reg,constrained_intra_pred_flag,
	rem_intra4x4_pred_mode,prev_intra4x4_pred_mode_flag,Intra4x4PredMode_mbAddrB_dout,
	
	Intra4x4PredMode_CurrMb,
	Intra4x4PredMode_mbAddrB_cs_n,Intra4x4PredMode_mbAddrB_wr_n,Intra4x4PredMode_mbAddrB_rd_addr,
	Intra4x4PredMode_mbAddrB_wr_addr,Intra4x4PredMode_mbAddrB_din
	);
	input clk,reset_n;
	input [2:0] mb_pred_state;
	input [3:0] luma4x4BlkIdx;
	input [3:0] mb_num_h,mb_num_v;
	input [1:0] MBTypeGen_mbAddrA;
	input [21:0] MBTypeGen_mbAddrB_reg;
	input constrained_intra_pred_flag;
	input [2:0] rem_intra4x4_pred_mode;
	input prev_intra4x4_pred_mode_flag;
	input [15:0] Intra4x4PredMode_mbAddrB_dout;
	//input [8:0] pic_num;
	
	output [63:0] Intra4x4PredMode_CurrMb;
	output Intra4x4PredMode_mbAddrB_cs_n,Intra4x4PredMode_mbAddrB_wr_n;
	output [3:0] Intra4x4PredMode_mbAddrB_rd_addr,Intra4x4PredMode_mbAddrB_wr_addr;
	output [15:0] Intra4x4PredMode_mbAddrB_din; 
	
	reg Intra4x4PredMode_mbAddrB_cs_n,Intra4x4PredMode_mbAddrB_wr_n;
	reg [3:0] Intra4x4PredMode_mbAddrB_rd_addr,Intra4x4PredMode_mbAddrB_wr_addr;
	reg [15:0] Intra4x4PredMode_mbAddrB_din; 
		
	wire mbAddrA_availability;
	wire mbAddrB_availability; 
	wire mbAddrA;
	wire mbAddrB;
	wire [3:0] predIntra4x4PredMode;	//prediction mode obtained at `prev_intra4x4_pred_mode_flag_s
	reg dcOnlyPredictionFlag;
	reg [15:0] Intra4x4PredMode_mbAddrA;
	reg [63:0] Intra4x4PredMode_CurrMb;
	reg [3:0] Intra4x4PredModeA,Intra4x4PredModeB;
	
	reg [3:0] rem_Intra4x4PredMode;     //prediction mode obtained at `rem_intra4x4_pred_mode_s
	reg [3:0] predIntra4x4PredMode_reg; //the reg value of predIntra4x4PredMode
	
	
	reg [1:0] MBTypeGen_mbAddrB;
	always @ (mb_num_h or MBTypeGen_mbAddrB_reg)
		case (mb_num_h)
			0 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[1:0];
			1 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[3:2];
			2 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[5:4];
			3 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[7:6];
			4 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[9:8];
			5 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[11:10];
			6 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[13:12];
			7 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[15:14];
			8 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[17:16];
			9 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[19:18];
			10:MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[21:20];
			default:MBTypeGen_mbAddrB <= 0;
		endcase

	//neighboring block decoding for Intra4x4 prediction mode,NO mapping from Blk4x4 order --> raster order
	assign mbAddrA_availability = (luma4x4BlkIdx == 0 || luma4x4BlkIdx == 2 
	|| luma4x4BlkIdx == 8 || luma4x4BlkIdx == 10)? ((mb_num_h == 0)? 1'b0:1'b1):1'b1;
	
	assign mbAddrB_availability = (luma4x4BlkIdx == 0 || luma4x4BlkIdx == 1 
	|| luma4x4BlkIdx == 4 || luma4x4BlkIdx == 5)? ((mb_num_v == 0)? 1'b0:1'b1):1'b1;
	
	assign mbAddrA = (luma4x4BlkIdx == 0 || luma4x4BlkIdx == 2 || luma4x4BlkIdx == 8 
	|| luma4x4BlkIdx == 10)? 1'b0:1'b1;	//0:left MB;1:curr MB
	
	assign mbAddrB = (luma4x4BlkIdx == 0 || luma4x4BlkIdx == 1 || luma4x4BlkIdx == 4 
	|| luma4x4BlkIdx == 5)? 1'b0:1'b1;	//0:upper MB;1:curr MB	
	
	//dcOnlyPredictionFlag	
	always @ (mb_pred_state or mbAddrA_availability or mbAddrB_availability or mbAddrA or mbAddrB or 
		MBTypeGen_mbAddrA or MBTypeGen_mbAddrB or constrained_intra_pred_flag)
		if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s)
			begin
				if (mbAddrA_availability == 0)
					dcOnlyPredictionFlag <= 1;
				else if (mbAddrB_availability == 0)
					dcOnlyPredictionFlag <= 1;
				else if (mbAddrA == 0 && MBTypeGen_mbAddrA < 2 && constrained_intra_pred_flag == 1)
					dcOnlyPredictionFlag <= 1;
				else if (mbAddrB == 0 && MBTypeGen_mbAddrB < 2 && constrained_intra_pred_flag == 1)
					dcOnlyPredictionFlag <= 1;
				else 
					dcOnlyPredictionFlag <= 0;
			end
		else
			dcOnlyPredictionFlag <= 0;
	//Intra4x4PredModeA		
	always @ (mb_pred_state or dcOnlyPredictionFlag or mbAddrA or mbAddrA_availability or MBTypeGen_mbAddrA 
		or Intra4x4PredMode_mbAddrA or Intra4x4PredMode_CurrMb or luma4x4BlkIdx)
		if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s)
			begin
				if (dcOnlyPredictionFlag == 1)
					Intra4x4PredModeA <= 2;
				else if (mbAddrA_availability == 1 && mbAddrA == 0 && MBTypeGen_mbAddrA != `MB_addrA_addrB_Intra4x4)//not coded in Intra4x4
					Intra4x4PredModeA <= 2;
				else
					case (luma4x4BlkIdx)
						0 :Intra4x4PredModeA <= Intra4x4PredMode_mbAddrA[3:0];
						1 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[3:0];
						2 :Intra4x4PredModeA <= Intra4x4PredMode_mbAddrA[7:4];
						3 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[11:8];
						4 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[7:4];
						5 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[19:16];
						6 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[15:12];
						7 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[27:24];
						8 :Intra4x4PredModeA <= Intra4x4PredMode_mbAddrA[11:8];
						9 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[35:32];
						10:Intra4x4PredModeA <= Intra4x4PredMode_mbAddrA[15:12];
						11:Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[43:40];
						12:Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[39:36];
						13:Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[51:48];
						14:Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[47:44];
						15:Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[59:56];
					endcase
			end
		else
			Intra4x4PredModeA <= 0;	
	//Intra4x4PredModeB
	always @ (mb_pred_state or dcOnlyPredictionFlag or mbAddrB or mbAddrB_availability or MBTypeGen_mbAddrB 
		or Intra4x4PredMode_mbAddrB_dout or Intra4x4PredMode_CurrMb or luma4x4BlkIdx)
		if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s)
			begin
				if (dcOnlyPredictionFlag == 1)
					Intra4x4PredModeB <= 2;
				else if (mbAddrB_availability == 1 && mbAddrB == 0 && MBTypeGen_mbAddrB != `MB_addrA_addrB_Intra4x4)	//not coded in Intra4x4
					Intra4x4PredModeB <= 2;
				else
					case (luma4x4BlkIdx)
						0 :Intra4x4PredModeB <= Intra4x4PredMode_mbAddrB_dout[15:12];
						1 :Intra4x4PredModeB <= Intra4x4PredMode_mbAddrB_dout[11:8];
						2 :Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[3:0];
						3 :Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[7:4];
						4 :Intra4x4PredModeB <= Intra4x4PredMode_mbAddrB_dout[7:4];
						5 :Intra4x4PredModeB <= Intra4x4PredMode_mbAddrB_dout[3:0];
						6 :Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[19:16];
						7 :Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[23:20];
						8 :Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[11:8];
						9 :Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[15:12];
						10:Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[35:32];
						11:Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[39:36];
						12:Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[27:24];
						13:Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[31:28];
						14:Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[51:48];
						15:Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[55:52];
					endcase
			end
		else
			Intra4x4PredModeB <= 0;	
	//obtain prediction mode at prev_intra4x4_pred_mode_flag_s		
	assign predIntra4x4PredMode = (Intra4x4PredModeA < Intra4x4PredModeB)? Intra4x4PredModeA:Intra4x4PredModeB;
	always @ (posedge clk)
		if (reset_n == 0)
			predIntra4x4PredMode_reg <= 0;
		else if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s && prev_intra4x4_pred_mode_flag == 0)
			predIntra4x4PredMode_reg <= predIntra4x4PredMode;
	//obtain prediction mode at rem_intra4x4_pred_mode_s
	always @ (mb_pred_state or rem_intra4x4_pred_mode or predIntra4x4PredMode_reg)	
		if (mb_pred_state == `rem_intra4x4_pred_mode_s)
			rem_Intra4x4PredMode <= ({
1'b0,rem_intra4x4_pred_mode
} < predIntra4x4PredMode_reg)?
				{
1'b0,rem_intra4x4_pred_mode
}:(rem_intra4x4_pred_mode + 1);
		else
			rem_Intra4x4PredMode <= 0;
	//-----------------------------
	//Intra4x4PredMode_CurrMb write
	//-----------------------------
	always @ (posedge clk)
		if (reset_n == 0)
			Intra4x4PredMode_CurrMb <= 0;
		else if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s && prev_intra4x4_pred_mode_flag == 1)
			case (luma4x4BlkIdx)
				0 :Intra4x4PredMode_CurrMb[3:0]    <= predIntra4x4PredMode;
				1 :Intra4x4PredMode_CurrMb[7:4]    <= predIntra4x4PredMode;
				2 :Intra4x4PredMode_CurrMb[11:8]   <= predIntra4x4PredMode;
				3 :Intra4x4PredMode_CurrMb[15:12]  <= predIntra4x4PredMode;
				4 :Intra4x4PredMode_CurrMb[19:16]  <= predIntra4x4PredMode;
				5 :Intra4x4PredMode_CurrMb[23:20]  <= predIntra4x4PredMode;
				6 :Intra4x4PredMode_CurrMb[27:24]  <= predIntra4x4PredMode;
				7 :Intra4x4PredMode_CurrMb[31:28]  <= predIntra4x4PredMode;
				8 :Intra4x4PredMode_CurrMb[35:32]  <= predIntra4x4PredMode;
				9 :Intra4x4PredMode_CurrMb[39:36]  <= predIntra4x4PredMode;
				10 :Intra4x4PredMode_CurrMb[43:40] <= predIntra4x4PredMode;
				11 :Intra4x4PredMode_CurrMb[47:44] <= predIntra4x4PredMode;
				12 :Intra4x4PredMode_CurrMb[51:48] <= predIntra4x4PredMode; 
				13 :Intra4x4PredMode_CurrMb[55:52] <= predIntra4x4PredMode;
				14 :Intra4x4PredMode_CurrMb[59:56] <= predIntra4x4PredMode;
				15 :Intra4x4PredMode_CurrMb[63:60] <= predIntra4x4PredMode;
			endcase
		else if (mb_pred_state == `rem_intra4x4_pred_mode_s)
			case (luma4x4BlkIdx)
				0 :Intra4x4PredMode_CurrMb[3:0]    <= rem_Intra4x4PredMode;
				1 :Intra4x4PredMode_CurrMb[7:4]    <= rem_Intra4x4PredMode;
				2 :Intra4x4PredMode_CurrMb[11:8]   <= rem_Intra4x4PredMode;
				3 :Intra4x4PredMode_CurrMb[15:12]  <= rem_Intra4x4PredMode;
				4 :Intra4x4PredMode_CurrMb[19:16]  <= rem_Intra4
...
...
(Please download the complete source code to view)
			
...
Expand> <Close

Want complete source code? Download it here

Point(s): 1

Download
0 lines left, continue to read
Sponsored links

File list

Tips: You can preview the content of files by clicking file names^_^
Name Size Date
Beha_BitStream_ram.v1.16 kB30-04-08|11:58
BitStream_buffer.v11.65 kB30-04-08|11:58
BitStream_controller.v25.60 kB30-04-08|11:58
bitstream_gclk_gen.v12.67 kB30-04-08|11:58
BitStream_parser_FSM_gating.v27.58 kB30-04-08|11:58
bs_decoding.v45.34 kB30-04-08|11:58
cavlc_consumed_bits_decoding.v1.85 kB30-04-08|11:58
cavlc_decoder.v10.33 kB30-04-08|11:58
CodedBlockPattern_decoding.v5.83 kB30-04-08|11:58
dependent_variable_decoding.v2.42 kB30-04-08|11:58
DF_mem_ctrl.v29.69 kB30-04-08|11:58
DF_pipeline.v33.65 kB30-04-08|11:58
DF_reg_ctrl.v15.94 kB30-04-08|11:58
DF_top.v7.41 kB30-04-08|11:58
end_of_blk_decoding.v2.82 kB30-04-08|11:58
exp_golomb_decoding.v6.17 kB30-04-08|11:58
ext_frame_RAM0_wrapper.v5.09 kB30-04-08|11:58
ext_frame_RAM1_wrapper.v5.10 kB30-04-08|11:58
ext_RAM_ctrl.v3.46 kB30-04-08|11:58
H.264.cr.mti2.20 kB28-02-09|13:54
H.264.mpf55.79 kB28-02-09|00:05
heading_one_detector.v2.51 kB30-04-08|11:58
hybrid_pipeline_ctrl.v10.79 kB30-04-08|11:58
Inter_mv_decoding.v93.25 kB30-04-08|11:58
Inter_pred_CPE.v3.74 kB30-04-08|11:58
Inter_pred_LPE.v23.87 kB30-04-08|11:58
Inter_pred_pipeline.v33.29 kB30-04-08|11:58
Inter_pred_reg_ctrl.v124.27 kB30-04-08|11:58
Inter_pred_sliding_window.v130.18 kB30-04-08|11:58
Inter_pred_top.v28.66 kB30-04-08|11:58
Intra4x4_PredMode_decoding.v14.99 kB30-04-08|11:58
Intra_pred_PE.v69.16 kB30-04-08|11:58
Intra_pred_pipeline.v32.46 kB24-02-09|22:46
Intra_pred_reg_ctrl.v36.37 kB30-04-08|11:58
Intra_pred_top.v14.40 kB30-04-08|11:58
IQIT.v32.48 kB30-04-08|11:58
level_decoding.v7.45 kB30-04-08|11:58
nC_decoding.v30.47 kB30-04-08|11:58
nova.v8.19 kB30-04-08|11:58
nova_defines.v12.10 kB30-04-08|11:58
nova_tb.v2.92 kB30-04-08|11:58
NumCoeffTrailingOnes_decoding.v25.79 kB30-04-08|11:58
pc_decoding.v10.34 kB30-04-08|11:58
QP_decoding.v2.31 kB30-04-08|11:58
ram_async_1r_sync_1w.v2.71 kB30-04-08|11:58
ram_sync_1r_sync_1w.v3.01 kB30-04-08|11:58
reconstruction.v22.49 kB30-04-08|11:58
rec_DF_RAM0_96x32.v18.23 kB30-04-08|11:58
rec_DF_RAM0_wrapper.v1.73 kB30-04-08|11:58
rec_DF_RAM1_96x32.v18.23 kB30-04-08|11:58
rec_DF_RAM1_wrapper.v1.73 kB30-04-08|11:58
rec_DF_RAM_ctrl.v6.42 kB30-04-08|11:58
rec_gclk_gen.v16.68 kB30-04-08|11:58
Intra_pred_PE.areasrr10.14 kB22-02-09|14:06
Intra_pred_PE.edn2.76 MB22-02-09|14:06
Intra_pred_PE.fse0.00 B22-02-09|14:06
Intra_pred_PE.sdf2.05 MB22-02-09|14:06
Intra_pred_PE.srd1.03 MB22-02-09|14:06
Intra_pred_PE.srm1.61 MB22-02-09|14:06
Intra_pred_PE.srr34.82 kB22-02-09|14:06
Intra_pred_PE.srs102.69 kB22-02-09|14:06
Intra_pred_PE.tlg418.00 B22-02-09|14:06
Intra_pred_PE_sdc.sdc310.00 B22-02-09|14:06
Intra_pred_PE.msg0.00 B22-02-09|14:46
Intra_pred_PE.plg441.00 B22-02-09|14:06
run_decoding.v11.61 kB30-04-08|11:58
sum.v23.78 kB30-04-08|11:58
syntax_decoding.v24.94 kB30-04-08|11:58
timescale.v546.00 B30-04-08|11:58
total_zeros_decoding.v14.96 kB30-04-08|11:58
vsim.wlf32.00 kB24-02-09|16:06
_primary.dat73.20 kB24-02-09|15:26
_primary.vhd11.00 kB24-02-09|15:26
verilog.asm49.59 kB21-02-09|17:50
_primary.dat7.28 kB21-02-09|17:50
_primary.vhd1.23 kB21-02-09|17:50
verilog.asm275.78 kB24-02-09|15:27
_primary.dat39.36 kB24-02-09|15:27
_primary.vhd4.99 kB24-02-09|15:27
_primary.dat15.08 kB26-02-09|11:49
_primary.vhd3.73 kB26-02-09|11:49
_primary.dat17.38 kB26-02-09|11:49
_primary.vhd4.65 kB26-02-09|11:49
verilog.asm61.01 kB22-02-09|21:56
_primary.dat8.81 kB19-02-09|20:59
_primary.vhd3.04 kB22-02-09|21:56
verilog.asm15.53 kB24-02-09|15:27
_primary.dat1.24 kB24-02-09|15:27
_primary.vhd902.00 B24-02-09|15:27
_primary.dat986.00 B26-02-09|11:49
_primary.vhd419.00 B26-02-09|11:49
_primary.dat1.40 kB26-02-09|11:49
_primary.vhd749.00 B26-02-09|11:49
_primary.dat328.00 B26-02-09|11:49
_primary.vhd307.00 B26-02-09|11:49
_primary.dat687.00 B26-02-09|11:49
_primary.vhd291.00 B26-02-09|11:49
_primary.dat1.73 kB26-02-09|11:24
_primary.vhd585.00 B26-02-09|11:24
_info2.66 kB26-02-09|11:49
syntmp0.00 B22-02-09|14:46
@inter_pred_reg_ctrl0.00 B24-02-09|15:26
@intra4x4_@pred@mode_decoding0.00 B21-02-09|17:50
@intra_pred_@p@e0.00 B24-02-09|15:27
@intra_pred_pipeline0.00 B26-02-09|11:49
@intra_pred_reg_ctrl0.00 B26-02-09|11:49
@intra_pred_top0.00 B22-02-09|21:56
@p@e0.00 B24-02-09|15:27
main_seed_precomputation0.00 B26-02-09|11:49
plane_@h@v_precomputation0.00 B26-02-09|11:49
plane_a_precomputation0.00 B26-02-09|11:49
plane_bc_precomputation0.00 B26-02-09|11:49
ram_sync_1r_sync_1w0.00 B26-02-09|11:24
_temp0.00 B26-02-09|11:49
rev_10.00 B22-02-09|14:06
work0.00 B26-02-09|11:49
H.2640.00 B08-03-09|19:18
...
Sponsored links

Intra4x4_PredMode_decoding.v (808.37 kB)

Need 1 point
Your Point(s)

Your Point isn't enough.

Get point immediately by PayPal

More(Debit card / Credit card / PayPal Credit / Online Banking)

Submit your source codes. Get more point

LOGIN

Don't have an account? Register now
Need any help?
Mail to: support@codeforge.com

切换到中文版?

CodeForge Chinese Version
CodeForge English Version

Where are you going?

^_^"Oops ...

Sorry!This guy is mysterious, its blog hasn't been opened, try another, please!
OK

Warm tip!

CodeForge to FavoriteFavorite by Ctrl+D