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Inter_pred_sliding_window.v ( File view )

From:H264 Verilog
  • By culourwq 2016-05-23
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			//--------------------------------------------------------------------------------------------------
// Design    : nova
// Author(s) : Ke Xu
// Email	   : eexuke@yahoo.com
// File      : Inter_pred_sliding_window.v
// Generated : Oct 25, 2005
// Copyright (C) 2008 Ke Xu                
//-------------------------------------------------------------------------------------------------
// Description 
// Prepare the appropriate registers for Inter prediction (luma & chroma) 
// 1)Luma:horizontal window 6x9,vertical window 1x9
// 2)Chroma:window 2x2
//-------------------------------------------------------------------------------------------------

// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "nova_defines.v"

module Inter_pred_sliding_window (IsInterLuma,IsInterChroma,Is_InterChromaCopy,mv_below8x8_curr,
	pos_FracL,blk4x4_rec_counter_1to0,blk4x4_inter_calculate_counter,
	Inter_ref_00_00,Inter_ref_01_00,Inter_ref_02_00,Inter_ref_03_00,Inter_ref_04_00,Inter_ref_05_00,
	Inter_ref_06_00,Inter_ref_07_00,Inter_ref_08_00,Inter_ref_09_00,Inter_ref_10_00,Inter_ref_11_00,Inter_ref_12_00,
	Inter_ref_00_01,Inter_ref_01_01,Inter_ref_02_01,Inter_ref_03_01,Inter_ref_04_01,Inter_ref_05_01,
	Inter_ref_06_01,Inter_ref_07_01,Inter_ref_08_01,Inter_ref_09_01,Inter_ref_10_01,Inter_ref_11_01,Inter_ref_12_01,
	Inter_ref_00_02,Inter_ref_01_02,Inter_ref_02_02,Inter_ref_03_02,Inter_ref_04_02,Inter_ref_05_02,
	Inter_ref_06_02,Inter_ref_07_02,Inter_ref_08_02,Inter_ref_09_02,Inter_ref_10_02,Inter_ref_11_02,Inter_ref_12_02,
	Inter_ref_00_03,Inter_ref_01_03,Inter_ref_02_03,Inter_ref_03_03,Inter_ref_04_03,Inter_ref_05_03,
	Inter_ref_06_03,Inter_ref_07_03,Inter_ref_08_03,Inter_ref_09_03,Inter_ref_10_03,Inter_ref_11_03,Inter_ref_12_03,
	Inter_ref_00_04,Inter_ref_01_04,Inter_ref_02_04,Inter_ref_03_04,Inter_ref_04_04,Inter_ref_05_04,
	Inter_ref_06_04,Inter_ref_07_04,Inter_ref_08_04,Inter_ref_09_04,Inter_ref_10_04,Inter_ref_11_04,Inter_ref_12_04,
	Inter_ref_00_05,Inter_ref_01_05,Inter_ref_02_05,Inter_ref_03_05,Inter_ref_04_05,Inter_ref_05_05,
	Inter_ref_06_05,Inter_ref_07_05,Inter_ref_08_05,Inter_ref_09_05,Inter_ref_10_05,Inter_ref_11_05,Inter_ref_12_05,
	Inter_ref_00_06,Inter_ref_01_06,Inter_ref_02_06,Inter_ref_03_06,Inter_ref_04_06,Inter_ref_05_06,
	Inter_ref_06_06,Inter_ref_07_06,Inter_ref_08_06,Inter_ref_09_06,Inter_ref_10_06,Inter_ref_11_06,Inter_ref_12_06,
	Inter_ref_00_07,Inter_ref_01_07,Inter_ref_02_07,Inter_ref_03_07,Inter_ref_04_07,Inter_ref_05_07,
	Inter_ref_06_07,Inter_ref_07_07,Inter_ref_08_07,Inter_ref_09_07,Inter_ref_10_07,Inter_ref_11_07,Inter_ref_12_07,
	Inter_ref_00_08,Inter_ref_01_08,Inter_ref_02_08,Inter_ref_03_08,Inter_ref_04_08,Inter_ref_05_08,
	Inter_ref_06_08,Inter_ref_07_08,Inter_ref_08_08,Inter_ref_09_08,Inter_ref_10_08,Inter_ref_11_08,Inter_ref_12_08,
	Inter_ref_00_09,Inter_ref_01_09,Inter_ref_02_09,Inter_ref_03_09,Inter_ref_04_09,Inter_ref_05_09,
	Inter_ref_06_09,Inter_ref_07_09,Inter_ref_08_09,Inter_ref_09_09,Inter_ref_10_09,Inter_ref_11_09,Inter_ref_12_09,
	Inter_ref_00_10,Inter_ref_01_10,Inter_ref_02_10,Inter_ref_03_10,Inter_ref_04_10,Inter_ref_05_10,
	Inter_ref_06_10,Inter_ref_07_10,Inter_ref_08_10,Inter_ref_09_10,Inter_ref_10_10,Inter_ref_11_10,Inter_ref_12_10,
	Inter_ref_00_11,Inter_ref_01_11,Inter_ref_02_11,Inter_ref_03_11,Inter_ref_04_11,Inter_ref_05_11,
	Inter_ref_06_11,Inter_ref_07_11,Inter_ref_08_11,Inter_ref_09_11,Inter_ref_10_11,Inter_ref_11_11,Inter_ref_12_11,
	Inter_ref_00_12,Inter_ref_01_12,Inter_ref_02_12,Inter_ref_03_12,Inter_ref_04_12,Inter_ref_05_12,
	Inter_ref_06_12,Inter_ref_07_12,Inter_ref_08_12,Inter_ref_09_12,Inter_ref_10_12,Inter_ref_11_12,Inter_ref_12_12, 
	
	Inter_pix_copy0,Inter_pix_copy1,Inter_pix_copy2,Inter_pix_copy3,
	Inter_H_window_0_0,Inter_H_window_1_0,Inter_H_window_2_0,Inter_H_window_3_0,Inter_H_window_4_0,Inter_H_window_5_0,
	Inter_H_window_0_1,Inter_H_window_1_1,Inter_H_window_2_1,Inter_H_window_3_1,Inter_H_window_4_1,Inter_H_window_5_1,
	Inter_H_window_0_2,Inter_H_window_1_2,Inter_H_window_2_2,Inter_H_window_3_2,Inter_H_window_4_2,Inter_H_window_5_2,
	Inter_H_window_0_3,Inter_H_window_1_3,Inter_H_window_2_3,Inter_H_window_3_3,Inter_H_window_4_3,Inter_H_window_5_3,
	Inter_H_window_0_4,Inter_H_window_1_4,Inter_H_window_2_4,Inter_H_window_3_4,Inter_H_window_4_4,Inter_H_window_5_4,
	Inter_H_window_0_5,Inter_H_window_1_5,Inter_H_window_2_5,Inter_H_window_3_5,Inter_H_window_4_5,Inter_H_window_5_5,
	Inter_H_window_0_6,Inter_H_window_1_6,Inter_H_window_2_6,Inter_H_window_3_6,Inter_H_window_4_6,Inter_H_window_5_6,
	Inter_H_window_0_7,Inter_H_window_1_7,Inter_H_window_2_7,Inter_H_window_3_7,Inter_H_window_4_7,Inter_H_window_5_7,
	Inter_H_window_0_8,Inter_H_window_1_8,Inter_H_window_2_8,Inter_H_window_3_8,Inter_H_window_4_8,Inter_H_window_5_8,
	Inter_V_window_0,Inter_V_window_1,Inter_V_window_2,Inter_V_window_3,Inter_V_window_4,
	Inter_V_window_5,Inter_V_window_6,Inter_V_window_7,Inter_V_window_8,
	Inter_C_window_0_0,Inter_C_window_1_0,Inter_C_window_2_0,
	Inter_C_window_0_1,Inter_C_window_1_1,Inter_C_window_2_1,
	Inter_C_window_0_2,Inter_C_window_1_2,Inter_C_window_2_2,
	Inter_bi_window_0,Inter_bi_window_1,Inter_bi_window_2,Inter_bi_window_3);
	input IsInterLuma;
	input IsInterChroma;
	input Is_InterChromaCopy;
	input mv_below8x8_curr;
	input [3:0] pos_FracL;
	input [1:0] blk4x4_rec_counter_1to0;
	input [3:0] blk4x4_inter_calculate_counter;
	
	input [7:0] Inter_ref_00_00,Inter_ref_01_00,Inter_ref_02_00,Inter_ref_03_00,Inter_ref_04_00,Inter_ref_05_00;
	input [7:0] Inter_ref_06_00,Inter_ref_07_00,Inter_ref_08_00,Inter_ref_09_00,Inter_ref_10_00,Inter_ref_11_00,Inter_ref_12_00;
	input [7:0] Inter_ref_00_01,Inter_ref_01_01,Inter_ref_02_01,Inter_ref_03_01,Inter_ref_04_01,Inter_ref_05_01;
	input [7:0] Inter_ref_06_01,Inter_ref_07_01,Inter_ref_08_01,Inter_ref_09_01,Inter_ref_10_01,Inter_ref_11_01,Inter_ref_12_01;
	input [7:0] Inter_ref_00_02,Inter_ref_01_02,Inter_ref_02_02,Inter_ref_03_02,Inter_ref_04_02,Inter_ref_05_02;
	input [7:0] Inter_ref_06_02,Inter_ref_07_02,Inter_ref_08_02,Inter_ref_09_02,Inter_ref_10_02,Inter_ref_11_02,Inter_ref_12_02;
	input [7:0] Inter_ref_00_03,Inter_ref_01_03,Inter_ref_02_03,Inter_ref_03_03,Inter_ref_04_03,Inter_ref_05_03;
	input [7:0] Inter_ref_06_03,Inter_ref_07_03,Inter_ref_08_03,Inter_ref_09_03,Inter_ref_10_03,Inter_ref_11_03,Inter_ref_12_03;
	input [7:0] Inter_ref_00_04,Inter_ref_01_04,Inter_ref_02_04,Inter_ref_03_04,Inter_ref_04_04,Inter_ref_05_04;
	input [7:0] Inter_ref_06_04,Inter_ref_07_04,Inter_ref_08_04,Inter_ref_09_04,Inter_ref_10_04,Inter_ref_11_04,Inter_ref_12_04;
	input [7:0] Inter_ref_00_05,Inter_ref_01_05,Inter_ref_02_05,Inter_ref_03_05,Inter_ref_04_05,Inter_ref_05_05;
	input [7:0] Inter_ref_06_05,Inter_ref_07_05,Inter_ref_08_05,Inter_ref_09_05,Inter_ref_10_05,Inter_ref_11_05,Inter_ref_12_05;
	input [7:0] Inter_ref_00_06,Inter_ref_01_06,Inter_ref_02_06,Inter_ref_03_06,Inter_ref_04_06,Inter_ref_05_06;
	input [7:0] Inter_ref_06_06,Inter_ref_07_06,Inter_ref_08_06,Inter_ref_09_06,Inter_ref_10_06,Inter_ref_11_06,Inter_ref_12_06;
	input [7:0] Inter_ref_00_07,Inter_ref_01_07,Inter_ref_02_07,Inter_ref_03_07,Inter_ref_04_07,Inter_ref_05_07;
	input [7:0] Inter_ref_06_07,Inter_ref_07_07,Inter_ref_08_07,Inter_ref_09_07,Inter_ref_10_07,Inter_ref_11_07,Inter_ref_12_07;
	input [7:0] Inter_ref_00_08,Inter_ref_01_08,Inter_ref_02_08,Inter_ref_03_08,Inter_ref_04_08,Inter_ref_05_08;
	input [7:0] Inter_ref_06_08,Inter_ref_07_08,Inter_ref_08_08,Inter_ref_09_08,Inter_ref_10_08,Inter_ref_11_08,Inter_ref_12_08;
	input [7:0] Inter_ref_00_09,Inter_ref_01_09,Inter_ref_02_09,Inter_ref_03_09,Inter_ref_04_09,Inter_ref_05_09;
	input [7:0] Inter_ref_06_09,Inter_ref_07_09,Inter_ref_08_09,Inter_ref_09_09,Inter_ref_10_09,Inter_ref_11_09,Inter_ref_12_09;
	input [7:0] Inter_ref_00_10,Inter_ref_01_10,Inter_ref_02_10,Inter_ref_03_10,Inter_ref_04_10,Inter_ref_05_10;
	input [7:0] Inter_ref_06_10,Inter_ref_07_10,Inter_ref_08_10,Inter_ref_09_10,Inter_ref_10_10,Inter_ref_11_10,Inter_ref_12_10;
	input [7:0] Inter_ref_00_11,Inter_ref_01_11,Inter_ref_02_11,Inter_ref_03_11,Inter_ref_04_11,Inter_ref_05_11;
	input [7:0] Inter_ref_06_11,Inter_ref_07_11,Inter_ref_08_11,Inter_ref_09_11,Inter_ref_10_11,Inter_ref_11_11,Inter_ref_12_11;
	input [7:0] Inter_ref_00_12,Inter_ref_01_12,Inter_ref_02_12,Inter_ref_03_12,Inter_ref_04_12,Inter_ref_05_12;
	input [7:0] Inter_ref_06_12,Inter_ref_07_12,Inter_ref_08_12,Inter_ref_09_12,Inter_ref_10_12,Inter_ref_11_12,Inter_ref_12_12; 
	
	output [7:0] Inter_pix_copy0,Inter_pix_copy1,Inter_pix_copy2,Inter_pix_copy3;
	output [7:0] Inter_H_window_0_0,Inter_H_window_1_0,Inter_H_window_2_0,Inter_H_window_3_0,Inter_H_window_4_0,Inter_H_window_5_0;
	output [7:0] Inter_H_window_0_1,Inter_H_window_1_1,Inter_H_window_2_1,Inter_H_window_3_1,Inter_H_window_4_1,Inter_H_window_5_1;
	output [7:0] Inter_H_window_0_2,Inter_H_window_1_2,Inter_H_window_2_2,Inter_H_window_3_2,Inter_H_window_4_2,Inter_H_window_5_2;
	output [7:0] Inter_H_window_0_3,Inter_H_window_1_3,Inter_H_window_2_3,Inter_H_window_3_3,Inter_H_window_4_3,Inter_H_window_5_3;
	output [7:0] Inter_H_window_0_4,Inter_H_window_1_4,Inter_H_window_2_4,Inter_H_window_3_4,Inter_H_window_4_4,Inter_H_window_5_4;
	output [7:0] Inter_H_window_0_5,Inter_H_window_1_5,Inter_H_window_2_5,Inter_H_window_3_5,Inter_H_window_4_5,Inter_H_window_5_5;
	output [7:0] Inter_H_window_0_6,Inter_H_window_1_6,Inter_H_window_2_6,Inter_H_window_3_6,Inter_H_window_4_6,Inter_H_window_5_6;
	output [7:0] Inter_H_window_0_7,Inter_H_window_1_7,Inter_H_window_2_7,Inter_H_window_3_7,Inter_H_window_4_7,Inter_H_window_5_7;
	output [7:0] Inter_H_window_0_8,Inter_H_window_1_8,Inter_H_window_2_8,Inter_H_window_3_8,Inter_H_window_4_8,Inter_H_window_5_8;
	output [7:0] Inter_V_window_0,Inter_V_window_1,Inter_V_window_2,Inter_V_window_3,Inter_V_window_4;
	output [7:0] Inter_V_window_5,Inter_V_window_6,Inter_V_window_7,Inter_V_window_8;
	output [7:0] Inter_C_window_0_0,Inter_C_window_1_0,Inter_C_window_2_0;
	output [7:0] Inter_C_window_0_1,Inter_C_window_1_1,Inter_C_window_2_1;
	output [7:0] Inter_C_window_0_2,Inter_C_window_1_2,Inter_C_window_2_2;
	output [7:0] Inter_bi_window_0,Inter_bi_window_1,Inter_bi_window_2,Inter_bi_window_3;
	
	reg [7:0] Inter_pix_copy0,Inter_pix_cop
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Beha_BitStream_ram.v1.16 kB30-04-08|11:58
BitStream_buffer.v11.65 kB30-04-08|11:58
BitStream_controller.v25.60 kB30-04-08|11:58
bitstream_gclk_gen.v12.67 kB30-04-08|11:58
BitStream_parser_FSM_gating.v27.58 kB30-04-08|11:58
bs_decoding.v45.34 kB30-04-08|11:58
cavlc_consumed_bits_decoding.v1.85 kB30-04-08|11:58
cavlc_decoder.v10.33 kB30-04-08|11:58
CodedBlockPattern_decoding.v5.83 kB30-04-08|11:58
dependent_variable_decoding.v2.42 kB30-04-08|11:58
DF_mem_ctrl.v29.69 kB30-04-08|11:58
DF_pipeline.v33.65 kB30-04-08|11:58
DF_reg_ctrl.v15.94 kB30-04-08|11:58
DF_top.v7.41 kB30-04-08|11:58
end_of_blk_decoding.v2.82 kB30-04-08|11:58
exp_golomb_decoding.v6.17 kB30-04-08|11:58
ext_frame_RAM0_wrapper.v5.09 kB30-04-08|11:58
ext_frame_RAM1_wrapper.v5.10 kB30-04-08|11:58
ext_RAM_ctrl.v3.46 kB30-04-08|11:58
H.264.cr.mti2.20 kB28-02-09|13:54
H.264.mpf55.79 kB28-02-09|00:05
heading_one_detector.v2.51 kB30-04-08|11:58
hybrid_pipeline_ctrl.v10.79 kB30-04-08|11:58
Inter_mv_decoding.v93.25 kB30-04-08|11:58
Inter_pred_CPE.v3.74 kB30-04-08|11:58
Inter_pred_LPE.v23.87 kB30-04-08|11:58
Inter_pred_pipeline.v33.29 kB30-04-08|11:58
Inter_pred_reg_ctrl.v124.27 kB30-04-08|11:58
Inter_pred_sliding_window.v130.18 kB30-04-08|11:58
Inter_pred_top.v28.66 kB30-04-08|11:58
Intra4x4_PredMode_decoding.v14.99 kB30-04-08|11:58
Intra_pred_PE.v69.16 kB30-04-08|11:58
Intra_pred_pipeline.v32.46 kB24-02-09|22:46
Intra_pred_reg_ctrl.v36.37 kB30-04-08|11:58
Intra_pred_top.v14.40 kB30-04-08|11:58
IQIT.v32.48 kB30-04-08|11:58
level_decoding.v7.45 kB30-04-08|11:58
nC_decoding.v30.47 kB30-04-08|11:58
nova.v8.19 kB30-04-08|11:58
nova_defines.v12.10 kB30-04-08|11:58
nova_tb.v2.92 kB30-04-08|11:58
NumCoeffTrailingOnes_decoding.v25.79 kB30-04-08|11:58
pc_decoding.v10.34 kB30-04-08|11:58
QP_decoding.v2.31 kB30-04-08|11:58
ram_async_1r_sync_1w.v2.71 kB30-04-08|11:58
ram_sync_1r_sync_1w.v3.01 kB30-04-08|11:58
reconstruction.v22.49 kB30-04-08|11:58
rec_DF_RAM0_96x32.v18.23 kB30-04-08|11:58
rec_DF_RAM0_wrapper.v1.73 kB30-04-08|11:58
rec_DF_RAM1_96x32.v18.23 kB30-04-08|11:58
rec_DF_RAM1_wrapper.v1.73 kB30-04-08|11:58
rec_DF_RAM_ctrl.v6.42 kB30-04-08|11:58
rec_gclk_gen.v16.68 kB30-04-08|11:58
Intra_pred_PE.areasrr10.14 kB22-02-09|14:06
Intra_pred_PE.edn2.76 MB22-02-09|14:06
Intra_pred_PE.fse0.00 B22-02-09|14:06
Intra_pred_PE.sdf2.05 MB22-02-09|14:06
Intra_pred_PE.srd1.03 MB22-02-09|14:06
Intra_pred_PE.srm1.61 MB22-02-09|14:06
Intra_pred_PE.srr34.82 kB22-02-09|14:06
Intra_pred_PE.srs102.69 kB22-02-09|14:06
Intra_pred_PE.tlg418.00 B22-02-09|14:06
Intra_pred_PE_sdc.sdc310.00 B22-02-09|14:06
Intra_pred_PE.msg0.00 B22-02-09|14:46
Intra_pred_PE.plg441.00 B22-02-09|14:06
run_decoding.v11.61 kB30-04-08|11:58
sum.v23.78 kB30-04-08|11:58
syntax_decoding.v24.94 kB30-04-08|11:58
timescale.v546.00 B30-04-08|11:58
total_zeros_decoding.v14.96 kB30-04-08|11:58
vsim.wlf32.00 kB24-02-09|16:06
_primary.dat73.20 kB24-02-09|15:26
_primary.vhd11.00 kB24-02-09|15:26
verilog.asm49.59 kB21-02-09|17:50
_primary.dat7.28 kB21-02-09|17:50
_primary.vhd1.23 kB21-02-09|17:50
verilog.asm275.78 kB24-02-09|15:27
_primary.dat39.36 kB24-02-09|15:27
_primary.vhd4.99 kB24-02-09|15:27
_primary.dat15.08 kB26-02-09|11:49
_primary.vhd3.73 kB26-02-09|11:49
_primary.dat17.38 kB26-02-09|11:49
_primary.vhd4.65 kB26-02-09|11:49
verilog.asm61.01 kB22-02-09|21:56
_primary.dat8.81 kB19-02-09|20:59
_primary.vhd3.04 kB22-02-09|21:56
verilog.asm15.53 kB24-02-09|15:27
_primary.dat1.24 kB24-02-09|15:27
_primary.vhd902.00 B24-02-09|15:27
_primary.dat986.00 B26-02-09|11:49
_primary.vhd419.00 B26-02-09|11:49
_primary.dat1.40 kB26-02-09|11:49
_primary.vhd749.00 B26-02-09|11:49
_primary.dat328.00 B26-02-09|11:49
_primary.vhd307.00 B26-02-09|11:49
_primary.dat687.00 B26-02-09|11:49
_primary.vhd291.00 B26-02-09|11:49
_primary.dat1.73 kB26-02-09|11:24
_primary.vhd585.00 B26-02-09|11:24
_info2.66 kB26-02-09|11:49
syntmp0.00 B22-02-09|14:46
@inter_pred_reg_ctrl0.00 B24-02-09|15:26
@intra4x4_@pred@mode_decoding0.00 B21-02-09|17:50
@intra_pred_@p@e0.00 B24-02-09|15:27
@intra_pred_pipeline0.00 B26-02-09|11:49
@intra_pred_reg_ctrl0.00 B26-02-09|11:49
@intra_pred_top0.00 B22-02-09|21:56
@p@e0.00 B24-02-09|15:27
main_seed_precomputation0.00 B26-02-09|11:49
plane_@h@v_precomputation0.00 B26-02-09|11:49
plane_a_precomputation0.00 B26-02-09|11:49
plane_bc_precomputation0.00 B26-02-09|11:49
ram_sync_1r_sync_1w0.00 B26-02-09|11:24
_temp0.00 B26-02-09|11:49
rev_10.00 B22-02-09|14:06
work0.00 B26-02-09|11:49
H.2640.00 B08-03-09|19:18
...
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Inter_pred_sliding_window.v (808.37 kB)

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