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  • By culourwq 2016-05-23
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			//--------------------------------------------------------------------------------------------------
// Design    : nova
// Author(s) : Ke Xu
// Email	   : eexuke@yahoo.com
// File      : IQIT.v
// Generated : June 18, 2005
// Copyright (C) 2008 Ke Xu                
//-------------------------------------------------------------------------------------------------
// Description 
// Decoding the residual information
// 1.The res_mb_bypass | DConly | allzero signals should be decoded first
// 2.For DC coefficients,IDCT    --> rescale
// 3.For AC coefficients,rescale --> IDCT   --> rounding
// 4.coeffLevel:zig-zag order
//   OneD_output,TwoD_output,DC_output,rescale_output,rounding_output:raster-scan order
// 5.Input coeffLevel_ext_0 ~ 15 are 2's complement,but with zig-zag order
//-------------------------------------------------------------------------------------------------
// Revise log 
// 1.March 27,2006
// DC_output: 0 ~ 15:for luma DC, 0 ~ 3:for Chroma Cb DC, 4 ~ 7:for Chroma Cr DC
// 2.March 28,2006
// 1)For Intra16x16ACLevel and chroma AC,the first coeff of IDCT is DC value, the following coeffLevel_ext_0 ~ 14 should be moved backward 1 space and coeffLevel_ext_15 is abandoned
// 2)There are some blocks which have zero DC coeff but non-zero AC coeff. Additional signals as res_LumaDCBlk_IsZero,res_ChromaDCBlk_Cb_IsZero,res_ChromaDCBlk_Cr_IsZero are added to deal with such special case  
//-------------------------------------------------------------------------------------------------

// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "nova_defines.v"

module IQIT (clk,reset_n,TotalCoeff,blk4x4_rec_counter,
	gclk_1D,gclk_2D,gclk_rescale,gclk_rounding,
	residual_state,cavlc_decoder_state,
	end_of_one_residual_block,end_of_NonZeroCoeff_CAVLC,
	QPy,QPc,i4x4_CbCr,
	coeffLevel_ext_0, coeffLevel_ext_1, coeffLevel_ext_2, coeffLevel_ext_3, 
	coeffLevel_ext_4, coeffLevel_ext_5, coeffLevel_ext_6, coeffLevel_ext_7,
	coeffLevel_ext_8, coeffLevel_ext_9, coeffLevel_ext_10,coeffLevel_ext_11,
	coeffLevel_ext_12,coeffLevel_ext_13,coeffLevel_ext_14,coeffLevel_ext_15,
	
	OneD_counter,TwoD_counter,rescale_counter,rounding_counter,
	curr_DC_IsZero,curr_DC_scaled,
	rounding_output_0,rounding_output_1,rounding_output_2,rounding_output_3,
	rounding_output_4,rounding_output_5,rounding_output_6,rounding_output_7,
	rounding_output_8,rounding_output_9,rounding_output_10,rounding_output_11,
	rounding_output_12,rounding_output_13,rounding_output_14,rounding_output_15,
	end_of_ACBlk4x4_IQIT,end_of_DCBlk_IQIT
	);
	input clk,reset_n;
	input [4:0] TotalCoeff;
	input [4:0] blk4x4_rec_counter;
	input gclk_1D;
	input gclk_2D;
	input gclk_rescale;
	input gclk_rounding;
	input [3:0] residual_state;
	input [3:0] cavlc_decoder_state;
	input end_of_one_residual_block;
	input end_of_NonZeroCoeff_CAVLC;
	input [5:0] QPy;
	input [5:0] QPc;
	input [1:0] i4x4_CbCr;
	input [15:0] coeffLevel_ext_0, coeffLevel_ext_1, coeffLevel_ext_2, coeffLevel_ext_3;
	input [15:0] coeffLevel_ext_4, coeffLevel_ext_5, coeffLevel_ext_6, coeffLevel_ext_7; 
	input [15:0] coeffLevel_ext_8, coeffLevel_ext_9, coeffLevel_ext_10,coeffLevel_ext_11;
	input [15:0] coeffLevel_ext_12,coeffLevel_ext_13,coeffLevel_ext_14,coeffLevel_ext_15; 
	
	
	output [2:0] OneD_counter;
	output [2:0] TwoD_counter;
	output [2:0] rescale_counter;
	output [2:0] rounding_counter;
	output curr_DC_IsZero;
	output [8:0] curr_DC_scaled;
	output [8:0] rounding_output_0, rounding_output_1, rounding_output_2, rounding_output_3;
	output [8:0] rounding_output_4, rounding_output_5, rounding_output_6, rounding_output_7;
	output [8:0] rounding_output_8, rounding_output_9, rounding_output_10,rounding_output_11;
	output [8:0] rounding_output_12,rounding_output_13,rounding_output_14,rounding_output_15;
	output end_of_ACBlk4x4_IQIT;	//end of IQIT of one blk4x4 AC
	output end_of_DCBlk_IQIT; 		//end of IQIT of one blk4x4/blk2x2 DC
	
	reg [8:0] rounding_output_0, rounding_output_1, rounding_output_2, rounding_output_3;
	reg [8:0] rounding_output_4, rounding_output_5, rounding_output_6, rounding_output_7;
	reg [8:0] rounding_output_8, rounding_output_9, rounding_output_10,rounding_output_11;
	reg [8:0] rounding_output_12,rounding_output_13,rounding_output_14,rounding_output_15;
	
	reg [2:0] OneD_counter;
	reg [2:0] TwoD_counter;
	reg [2:0] rescale_counter;
	reg [2:0] rounding_counter;
	reg [4:0] LevelScale_DC;
	reg [4:0] LevelScale_AC [3:0];
	reg [15:0] butterfly_D0,butterfly_D1,butterfly_D2,butterfly_D3;
	reg [15:0] mult0_a,mult1_a,mult2_a,mult3_a;
	reg IsLeftShift;
	reg [3:0] shift_len;
	reg [15:0] OneD_output [15:0];
	reg [15:0] TwoD_output [3:0];
	reg [15:0] rescale_output [3:0];
	reg [15:0] DC_output [15:0];
		
	wire IsHadamard;
	wire [5:0] QP;
	wire [2:0] QPmod6;
	wire [3:0] QPdiv6;
	wire [15:0] butterfly_F0,butterfly_F1,butterfly_F2,butterfly_F3;
	wire [4:0] LevelScale [3:0];
	wire [15:0] product0,product1,product2,product3;
	wire [15:0] shift_output0,shift_output1,shift_output2,shift_output3;
	wire [15:0] before_rounding0,before_rounding1,before_rounding2,before_rounding3;
	wire [9:0] rounding_sum0,rounding_sum1,rounding_sum2,rounding_sum3;	
	
	//-----------------------------------------------------------------------------------
	// Zero-block-aware decoding
	//-----------------------------------------------------------------------------------
	//Whether DC block is zero
	reg res_LumaDCBlk_IsZero;      
	reg res_ChromaDCBlk_Cb_IsZero; 
	reg res_ChromaDCBlk_Cr_IsZero;
	
	always @ (posedge clk)
		if (reset_n == 1'b0)
			begin
	         	res_LumaDCBlk_IsZero      <= 1'b0;
	         	res_ChromaDCBlk_Cb_IsZero <= 1'b0;
	         	res_ChromaDCBlk_Cr_IsZero <= 1'b0;
			end
		else if (cavlc_decoder_state == `NumCoeffTrailingOnes_LUT)
	    	begin
				if (residual_state == `Intra16x16DCLevel_s)	     
					res_LumaDCBlk_IsZero <= (TotalCoeff == 0)? 1'b1:1'b0;
	      if (residual_state == `ChromaDCLevel_Cb_s)	
					res_ChromaDCBlk_Cb_IsZero <= (TotalCoeff == 0)? 1'b1:1'b0;
				if (residual_state == `ChromaDCLevel_Cr_s)	
					res_ChromaDCBlk_Cr_IsZero <= (TotalCoeff == 0)? 1'b1:1'b0;
	      	end
			  
	//Whether current DC from DC_output[15:0] is zero
	//If whole DC block are all zeros or current single DC is zero,curr_DC is assigned 0
	//If current blk4x4 doesn't need DC (e.g. LumaLevel_s), curr_DC is also assigned 0
	reg [15:0] curr_DC;
	reg [15:0] curr_DC_reg;
	always @ (posedge clk)
		if (reset_n == 1'b0)
			curr_DC_reg <= 0;
		else 
			curr_DC_reg <= curr_DC;
			
	always @ (residual_state or TotalCoeff or blk4x4_rec_counter or end_of_one_residual_block
		or res_LumaDCBlk_IsZero or res_ChromaDCBlk_Cb_IsZero or res_ChromaDCBlk_Cr_IsZero or curr_DC_reg  
		or DC_output[0]  or DC_output[1]  or DC_output[2]  or DC_output[3] 
		or DC_output[4]  or DC_output[5]  or DC_output[6]  or DC_output[7]
		or DC_output[8]  or DC_output[9]  or DC_output[10] or DC_output[11]
		or DC_output[12] or DC_output[13] or DC_output[14] or DC_output[15])
		if (residual_state == `Intra16x16ACLevel_0_s || (residual_state == `Intra16x16ACLevel_s && (end_of_one_residual_block && TotalCoeff == 0)))
			begin
				if (res_LumaDCBlk_IsZero == 1)	
					curr_DC <= 0;
				else
					case (blk4x4_rec_counter)
						0 :curr_DC <= DC_output[0];	1 :curr_DC <= DC_output[1];
						2 :curr_DC <= DC_output[2];	3 :curr_DC <= DC_output[3];
						4 :curr_DC <= DC_output[4];	5 :curr_DC <= DC_output[5];
						6 :curr_DC <= DC_output[6];	7 :curr_DC <= DC_output[7];
						8 :curr_DC <= DC_output[8];	9 :curr_DC <= DC_output[9];
						10:curr_DC <= DC_output[10];11:curr_DC <= DC_output[11];
						12:curr_DC <= DC_output[12];13:curr_DC <= DC_output[13];
						14:curr_DC <= DC_output[14];15:curr_DC <= DC_output[15];
						default:curr_DC <= curr_DC_reg;
					endcase
			end
		else if (residual_state == `ChromaACLevel_0_s || ((residual_state == `ChromaACLevel_Cb_s 
			|| residual_state == `ChromaACLevel_Cr_s) && (end_of_one_residual_block && TotalCoeff == 0)))
			begin
				if (blk4x4_rec_counter < 20)	//Cb
					begin
						if (res_ChromaDCBlk_Cb_IsZero == 1'b1)	
							curr_DC <= 0;
						else 
							case (blk4x4_rec_counter)
								16:curr_DC <= DC_output[0];17:curr_DC <= DC_output[1];
								18:curr_DC <= DC_output[2];19:curr_DC <= DC_output[3];
								default:curr_DC <= curr_DC_reg;
							endcase
					end
				else 							//Cr
					begin
						if (res_ChromaDCBlk_Cr_IsZero == 1'b1)	
							curr_DC <= 0;
						else 
							case (blk4x4_rec_counter)
								20:curr_DC <= DC_output[4];21:curr_DC <= DC_output[5];
								22:curr_DC <= DC_output[6];23:curr_DC <= DC_output[7];
								default:curr_DC <= curr_DC_reg;
							endcase
					end
			end
		else
			curr_DC <= curr_DC_reg;
	
	wire curr_DC_IsZero;
	assign curr_DC_IsZero = (curr_DC == 0);
	
	wire [15:0] curr_DC_tmp;
	wire [8:0]  curr_DC_scaled;
	assign curr_DC_tmp = curr_DC + 32;
	assign curr_DC_scaled = curr_DC_tmp[14:6];
	
	//-----------------------------------------------------------------------------------
	//residual type indicator
	//-----------------------------------------------------------------------------------
	wire res_DC;
	wire res_AC;
	wire res_luma;
	
	assign res_DC = (residual_state == `Intra16x16DCLevel_s || residual_state == `ChromaDCLevel_Cb_s || residual_state == `ChromaDCLevel_Cr_s); 
	assign res_AC = (residual_state != `rst_residual && !res_DC);
	assign res_luma   =	(residual_state == `Intra16x16DCLevel_s   || residual_state == `Intra16x16ACLevel_s ||
                       residual_state == `Intra16x16ACLevel_0_s || residual_state == `LumaLevel_s || residual_state == `LumaLevel_0_s);
	
	//1.OneD_counter:control the step of 1D in IDCT,4 cycles
	//	For ChromaDC IDCT,we combine the original 2x2 2D IDCT into a 4x4-like 1D IDCT
	//	ChromaDC: 1 cycle
	//	Others  : 4 cycles
	always @ (posedge gclk_1D or negedge reset_n)
		if (reset_n == 0)
			OneD_counter <= 0;
		else if (OneD_counter == 0)
			OneD_counter <= (residual_state == `ChromaDCLevel_Cb_s || residual_state == `ChromaDCLevel_Cr_s)? 3'b001:3'b100;
		else
			OneD_counter <= OneD_counter - 1;
			
	//2.TwoD_counter:control the step of 2D in IDCT,4 cycles
	//	ChromaDC: 0 cycle (All ChromDC transform done at 1D-DCT)
	//	Others  : 4 cycles
	always @ (posedge g
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syntmp0.00 B22-02-09|14:46
@inter_pred_reg_ctrl0.00 B24-02-09|15:26
@intra4x4_@pred@mode_decoding0.00 B21-02-09|17:50
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