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BitStream_controller.v ( File view )

From:H264 Verilog
  • By culourwq 2016-05-23
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			//--------------------------------------------------------------------------------------------------
// Design    : nova
// Author(s) : Ke Xu
// Email	   : eexuke@yahoo.com
// File      : BitStream_controller.v
// Generated : June 12,2005
// Copyright (C) 2008 Ke Xu                
//-------------------------------------------------------------------------------------------------
// Description 
// top module for bitstream controller
//-------------------------------------------------------------------------------------------------

// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "nova_defines.v"

module BitStream_controller (clk,reset_n,freq_ctrl0,freq_ctrl1,BitStream_buffer_input,pin_disable_DF,
	trigger_CAVLC,blk4x4_rec_counter,end_of_DCBlk_IQIT,end_of_one_blk4x4_sum,end_of_MB_DEC,gclk_end_of_MB_DEC,
	curr_DC_IsZero,
	
	BitStream_ram_ren,BitStream_ram_addr,pic_num,
	mb_type_general,mb_num_h,mb_num_v,NextMB_IsSkip,LowerMB_IsSkip,
	slice_data_state,residual_state,cavlc_decoder_state,
	end_of_one_residual_block,end_of_NonZeroCoeff_CAVLC,end_of_one_frame,
	Intra16x16_predmode,Intra4x4_predmode_CurrMb,Intra_chroma_predmode,
	QPy,QPc,i4x4_CbCr,slice_alpha_c0_offset_div2,slice_beta_offset_div2,
	CodedBlockPatternLuma,CodedBlockPatternChroma,TotalCoeff,
	Is_skip_run_entry,skip_mv_calc,disable_DF,
	coeffLevel_0,coeffLevel_1,coeffLevel_2, coeffLevel_3, coeffLevel_4, coeffLevel_5, coeffLevel_6, coeffLevel_7,
	coeffLevel_8,coeffLevel_9,coeffLevel_10,coeffLevel_11,coeffLevel_12,coeffLevel_13,coeffLevel_14,coeffLevel_15,
	mv_is16x16,mv_below8x8,
	mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3,mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3,
	end_of_BS_DEC,bs_V0,bs_V1,bs_V2,bs_V3,bs_H0,bs_H1,bs_H2,bs_H3,
	
	slice_header_s6
	);
	input clk,reset_n;
	input freq_ctrl0;
	input freq_ctrl1;
	input [15:0] BitStream_buffer_input;
	input pin_disable_DF;
	input trigger_CAVLC;
	input [4:0] blk4x4_rec_counter;
	input end_of_DCBlk_IQIT;
	input end_of_one_blk4x4_sum;
	input end_of_MB_DEC;
	input gclk_end_of_MB_DEC;
	input curr_DC_IsZero;
	
	output BitStream_ram_ren;
	output [16:0] BitStream_ram_addr;
	output [5:0] pic_num;
	
  output [3:0] mb_type_general;
	output [3:0] mb_num_h;
	output [3:0] mb_num_v;
	output NextMB_IsSkip;
	output LowerMB_IsSkip;
	output [3:0] slice_data_state;
	output [3:0] residual_state; 
	output [3:0] cavlc_decoder_state;
	output end_of_one_residual_block;
	output end_of_NonZeroCoeff_CAVLC;
	output end_of_one_frame;
	output [1:0] Intra16x16_predmode;
	output [63:0] Intra4x4_predmode_CurrMb;
	output [1:0] Intra_chroma_predmode;
	output [5:0] QPy;
	output [5:0] QPc;
	output [1:0] i4x4_CbCr;
	output [3:0] slice_alpha_c0_offset_div2;
	output [3:0] slice_beta_offset_div2;
	output [3:0] CodedBlockPatternLuma;
	output [1:0] CodedBlockPatternChroma;
	output [4:0] TotalCoeff;
	output Is_skip_run_entry;
	output skip_mv_calc;
	output disable_DF;
	output [8:0] coeffLevel_0, coeffLevel_1, coeffLevel_2,coeffLevel_3, coeffLevel_4, coeffLevel_5; 
	output [8:0] coeffLevel_6, coeffLevel_7, coeffLevel_8, coeffLevel_9,coeffLevel_10,coeffLevel_11;
	output [8:0] coeffLevel_12,coeffLevel_13,coeffLevel_14,coeffLevel_15;
	output mv_is16x16;
	output [3:0] mv_below8x8;
	output [31:0] mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3;
	output [31:0] mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3;
	output end_of_BS_DEC;
	output [11:0] bs_V0,bs_V1,bs_V2,bs_V3;
	output [11:0] bs_H0,bs_H1,bs_H2,bs_H3;
	
	output slice_header_s6;
	
	wire gclk_parser;
	wire gclk_nal;
	wire gclk_slice;
	wire gclk_sps;
	wire gclk_pps;
	wire gclk_slice_header;
	wire gclk_slice_data;
	wire gclk_residual;
	wire gclk_cavlc;
	wire gclk_bs_dec;
	wire gclk_Intra4x4PredMode_mbAddrB_RF;
	wire gclk_mvx_mbAddrB_RF;
	wire gclk_mvy_mbAddrB_RF;
	wire gclk_mvx_mbAddrC_RF;
	wire gclk_mvy_mbAddrC_RF;
	wire gclk_LumaLevel_mbAddrB_RF;
	wire gclk_ChromaLevel_Cb_mbAddrB_RF;
	wire gclk_ChromaLevel_Cr_mbAddrB_RF;
	wire [6:0] pc;
	wire [5:0] QPy,QPc;
	wire [3:0] CodedBlockPatternLuma;
	wire [1:0] CodedBlockPatternChroma;
	wire [8:0] coeffLevel_0, coeffLevel_1, coeffLevel_2,coeffLevel_3, coeffLevel_4, coeffLevel_5; 
	wire [8:0] coeffLevel_6, coeffLevel_7, coeffLevel_8, coeffLevel_9,coeffLevel_10,coeffLevel_11;
	wire [8:0] coeffLevel_12,coeffLevel_13,coeffLevel_14,coeffLevel_15;
	wire [63:0] Intra4x4PredMode_CurrMb;
	wire mv_is16x16;
	wire Is_skip_run_end;
	wire Is_skipMB_mv_calc;
	wire [31:0] mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3;
	wire [31:0] mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3;
	
	wire BitStream_buffer_valid_n;
	wire [15:0] BitStream_buffer_output;
	wire [1:0] parser_state;
	wire [2:0] nal_unit_state;
	wire [1:0] slice_layer_wo_partitioning_state;
	wire [3:0] slice_header_state;
	wire [2:0] ref_pic_list_reordering_state;
	wire [1:0] dec_ref_pic_marking_state;
	wire [3:0] slice_data_state;
	wire [1:0] sub_mb_pred_state;
	wire [2:0] mb_pred_state;
	wire [3:0] seq_parameter_set_state;
	wire [3:0] pic_parameter_set_state;
	wire [3:0] residual_state;
	wire [3:0] cavlc_decoder_state;
	wire [3:0] exp_golomb_len;
	wire [3:0] dependent_variable_len;
	wire [4:0] cavlc_consumed_bits_len;
	wire heading_one_en;
	wire [3:0] heading_one_pos;
	wire [7:0] exp_golomb_decoding_output;
	wire [9:0] dependent_variable_decoding_output;
	wire Intra4x4PredMode_mbAddrB_cs_n;
	wire Intra4x4PredMode_mbAddrB_wr_n;
	wire [3:0] Intra4x4PredMode_mbAddrB_rd_addr;
	wire [3:0] Intra4x4PredMode_mbAddrB_wr_addr;
	wire [15:0] Intra4x4PredMode_mbAddrB_din;
	wire [15:0] Intra4x4PredMode_mbAddrB_dout;
	wire mvx_mbAddrB_cs_n;
	wire mvy_mbAddrB_cs_n;
	wire mvx_mbAddrC_cs_n;
	wire mvy_mbAddrC_cs_n;
	wire mvx_mbAddrB_wr_n;
	wire mvy_mbAddrB_wr_n;
	wire mvx_mbAddrC_wr_n;
	wire mvy_mbAddrC_wr_n;
	wire [3:0] mvx_mbAddrB_rd_addr;
	wire [3:0] mvy_mbAddrB_rd_addr;
	wire [3:0] mvx_mbAddrC_rd_addr;
	wire [3:0] mvy_mbAddrC_rd_addr;
	wire [3:0] mvx_mbAddrB_wr_addr;
	wire [3:0] mvy_mbAddrB_wr_addr;
	wire [3:0] mvx_mbAddrC_wr_addr;
	wire [3:0] mvy_mbAddrC_wr_addr;
	wire [31:0] mvx_mbAddrA;
	wire [31:0] mvy_mbAddrA;
	wire [31:0] mvx_mbAddrB_din;
	wire [31:0] mvx_mbAddrB_dout;
	wire [31:0] mvy_mbAddrB_din;
	wire [31:0] mvy_mbAddrB_dout;
	wire [7:0] mvx_mbAddrC_din;
	wire [7:0] mvx_mbAddrC_dout;
	wire [7:0] mvy_mbAddrC_din;
	wire [7:0] mvy_mbAddrC_dout;
	wire end_of_NonZeroCoeff_CAVLC;
	wire start_code_prefix_found;
	wire [4:0] nal_unit_type;
	wire deblocking_filter_control_present_flag;
	wire [1:0] disable_deblocking_filter_idc;
	wire disable_DF;
	wire [6:0] mb_skip_run;
	wire [2:0] NumMbPart;
	wire [2:0] NumSubMbPart;
	wire [1:0] MBTypeGen_mbAddrA;
	wire MBTypeGen_mbAddrD;
	wire [21:0]MBTypeGen_mbAddrB_reg;
	wire [3:0] log2_max_frame_num_minus4;
	wire [3:0] log2_max_pic_order_cnt_lsb_minus4;
	wire constrained_intra_pred_flag;
	wire num_ref_idx_active_override_flag;
	wire [2:0] num_ref_idx_l0_active_minus1;
	wire [2:0] slice_type;
	wire [4:0] mb_type;
	wire [3:0] mb_type_general;
	wire [1:0] sub_mb_type;
	wire [5:0] pic_init_qp_minus26;
	wire [4:0] chroma_qp_index_offset;
	wire [2:0] rem_intra4x4_pred_mode;
	wire [7:0] mvd;
	wire prev_intra4x4_pred_mode_flag;
	wire cavlc_decoder_en;
	wire [5:0] pic_num;
	wire [6:0] mb_num;
	wire [3:0] mb_num_h;
	wire [3:0] mb_num_v;
	wire [3:0] luma4x4BlkIdx;
	wire [1:0] mbPartIdx;
	wire [1:0] subMbPartIdx;
	wire compIdx;
	wire suffix_length_initialized;
	wire IsRunLoop;
	wire [1:0] i8x8,i4x4;
	wire [1:0] i4x4_CbCr;
	wire [3:0] coeffNum;
	wire [3:0] i_level;
	wire [3:0] i_run;
	wire [3:0] i_TotalCoeff;
	wire [4:0] TotalCoeff;
	wire [1:0] TrailingOnes;
	wire [4:0] maxNumCoeff;
	wire [3:0] zerosLeft;
	wire [3:0] run;
	
	wire [1:0] Luma_8x8_AllZeroCoeff_mbAddrA;
	wire [19:0] LumaLevel_mbAddrA;
	wire [19:0] LumaLevel_CurrMb0,LumaLevel_CurrMb1,LumaLevel_CurrMb2,LumaLevel_CurrMb3;
	wire LumaLevel_mbAddrB_cs_n;
	wire [19:0] LumaLevel_mbAddrB_dout;
	wire ChromaLevel_Cb_mbAddrB_cs_n;
	wire ChromaLevel_Cr_mbAddrB_cs_n;
	wire [1:0] bs_dec_counter;
	wire [11:0] bs_V0,bs_V1,bs_V2,bs_V3;
	wire [11:0] bs_H0,bs_H1,bs_H2,bs_H3;
	wire mv_mbAddrB_rd_for_DF;
	
	BitStream_buffer BitStream_buffer (
		.clk(clk),
		.reset_n(reset_n),
		.BitStream_buffer_input(BitStream_buffer_input),
		.pc(pc),
		.BitStream_ram_ren(BitStream_ram_ren),
		.BitStream_buffer_valid_n(BitStream_buffer_valid_n),
		.BitStream_buffer_output(BitStream_buffer_output),
		.BitStream_ram_addr(BitStream_ram_addr)
		); 
	bitstream_gclk_gen bitstream_gclk_gen (
		.clk(clk),
		.reset_n(reset_n),
		.freq_ctrl0(freq_ctrl0),
		.freq_ctrl1(freq_ctrl1),
		.parser_state(parser_state),
		.nal_unit_state(nal_unit_state),
		.slice_layer_wo_partitioning_state(slice_layer_wo_partitioning_state),
		.slice_header_state(slice_header_state),
		.slice_data_state(slice_data_state),
		.seq_parameter_set_state(seq_parameter_set_state),
		.pic_parameter_set_state(pic_parameter_set_state),
		.residual_state(residual_state), 
		.cavlc_decoder_state(cavlc_decoder_state),
		.mb_num(mb_num),
		.TotalCoeff(TotalCoeff),
		.start_code_prefix_found(start_code_prefix_found),
		.pc_2to0(pc[2:0]),
		.deblocking_filter_control_present_flag(deblocking_filter_control_present_flag),
		.disable_deblocking_filter_idc(disable_deblocking_filter_idc),
		.end_of_one_residual_block(end_of_one_residual_block),
		.Intra4x4PredMode_mbAddrB_cs_n(Intra4x4PredMode_mbAddrB_cs_n),
		.mvx_mbAddrB_cs_n(mvx_mbAddrB_cs_n),
		.mvy_mbAddrB_cs_n(mvy_mbAddrB_cs_n),
		.mvx_mbAddrC_cs_n(mvx_mbAddrC_cs_n),
		.mvy_mbAddrC_cs_n(mvy_mbAddrC_cs_n),
		.LumaLevel_mbAddrB_cs_n(LumaLevel_mbAddrB_cs_n),
		.ChromaLevel_Cb_mbAddrB_cs_n(ChromaLevel_Cb_mbAddrB_cs_n),
		.ChromaLevel_Cr_mbAddrB_cs_n(ChromaLevel_Cr_mbAddrB_cs_n),
		.trigger_CAVLC(trigger_CAVLC),
		.blk4x4_rec_counter(blk4x4_rec_counter),
		.end_of_DCBlk_IQIT(end_of_DCBlk_IQIT),
		.end_of_one_blk4x4_sum(end_of_one_blk4x4_sum),
		.end_of_MB_DEC(end_of_MB_DEC), 
		.disable_DF(disable_DF),
		.bs_dec_counter(bs_dec_counter),
		
		.gclk_parser(gclk_parser),
		.gclk_nal(gclk_nal),
		.gclk_slice(gclk_slice),
		.gclk_sps(gclk_sps),
		.gclk_pps(gclk_pps),
		.gclk_slice_header(gclk_slice_header),
		.gclk_slice_data(gclk_slice_data),
		.gclk_residual(gclk_residual),
		.gclk_cavlc(gclk_cavlc),
		.gclk_Intra4x4PredMode_mbAddrB_RF(gclk_Intra4x4PredMode_mbAddrB_RF),
		.gclk_
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Name Size Date
Beha_BitStream_ram.v1.16 kB30-04-08|11:58
BitStream_buffer.v11.65 kB30-04-08|11:58
BitStream_controller.v25.60 kB30-04-08|11:58
bitstream_gclk_gen.v12.67 kB30-04-08|11:58
BitStream_parser_FSM_gating.v27.58 kB30-04-08|11:58
bs_decoding.v45.34 kB30-04-08|11:58
cavlc_consumed_bits_decoding.v1.85 kB30-04-08|11:58
cavlc_decoder.v10.33 kB30-04-08|11:58
CodedBlockPattern_decoding.v5.83 kB30-04-08|11:58
dependent_variable_decoding.v2.42 kB30-04-08|11:58
DF_mem_ctrl.v29.69 kB30-04-08|11:58
DF_pipeline.v33.65 kB30-04-08|11:58
DF_reg_ctrl.v15.94 kB30-04-08|11:58
DF_top.v7.41 kB30-04-08|11:58
end_of_blk_decoding.v2.82 kB30-04-08|11:58
exp_golomb_decoding.v6.17 kB30-04-08|11:58
ext_frame_RAM0_wrapper.v5.09 kB30-04-08|11:58
ext_frame_RAM1_wrapper.v5.10 kB30-04-08|11:58
ext_RAM_ctrl.v3.46 kB30-04-08|11:58
H.264.cr.mti2.20 kB28-02-09|13:54
H.264.mpf55.79 kB28-02-09|00:05
heading_one_detector.v2.51 kB30-04-08|11:58
hybrid_pipeline_ctrl.v10.79 kB30-04-08|11:58
Inter_mv_decoding.v93.25 kB30-04-08|11:58
Inter_pred_CPE.v3.74 kB30-04-08|11:58
Inter_pred_LPE.v23.87 kB30-04-08|11:58
Inter_pred_pipeline.v33.29 kB30-04-08|11:58
Inter_pred_reg_ctrl.v124.27 kB30-04-08|11:58
Inter_pred_sliding_window.v130.18 kB30-04-08|11:58
Inter_pred_top.v28.66 kB30-04-08|11:58
Intra4x4_PredMode_decoding.v14.99 kB30-04-08|11:58
Intra_pred_PE.v69.16 kB30-04-08|11:58
Intra_pred_pipeline.v32.46 kB24-02-09|22:46
Intra_pred_reg_ctrl.v36.37 kB30-04-08|11:58
Intra_pred_top.v14.40 kB30-04-08|11:58
IQIT.v32.48 kB30-04-08|11:58
level_decoding.v7.45 kB30-04-08|11:58
nC_decoding.v30.47 kB30-04-08|11:58
nova.v8.19 kB30-04-08|11:58
nova_defines.v12.10 kB30-04-08|11:58
nova_tb.v2.92 kB30-04-08|11:58
NumCoeffTrailingOnes_decoding.v25.79 kB30-04-08|11:58
pc_decoding.v10.34 kB30-04-08|11:58
QP_decoding.v2.31 kB30-04-08|11:58
ram_async_1r_sync_1w.v2.71 kB30-04-08|11:58
ram_sync_1r_sync_1w.v3.01 kB30-04-08|11:58
reconstruction.v22.49 kB30-04-08|11:58
rec_DF_RAM0_96x32.v18.23 kB30-04-08|11:58
rec_DF_RAM0_wrapper.v1.73 kB30-04-08|11:58
rec_DF_RAM1_96x32.v18.23 kB30-04-08|11:58
rec_DF_RAM1_wrapper.v1.73 kB30-04-08|11:58
rec_DF_RAM_ctrl.v6.42 kB30-04-08|11:58
rec_gclk_gen.v16.68 kB30-04-08|11:58
Intra_pred_PE.areasrr10.14 kB22-02-09|14:06
Intra_pred_PE.edn2.76 MB22-02-09|14:06
Intra_pred_PE.fse0.00 B22-02-09|14:06
Intra_pred_PE.sdf2.05 MB22-02-09|14:06
Intra_pred_PE.srd1.03 MB22-02-09|14:06
Intra_pred_PE.srm1.61 MB22-02-09|14:06
Intra_pred_PE.srr34.82 kB22-02-09|14:06
Intra_pred_PE.srs102.69 kB22-02-09|14:06
Intra_pred_PE.tlg418.00 B22-02-09|14:06
Intra_pred_PE_sdc.sdc310.00 B22-02-09|14:06
Intra_pred_PE.msg0.00 B22-02-09|14:46
Intra_pred_PE.plg441.00 B22-02-09|14:06
run_decoding.v11.61 kB30-04-08|11:58
sum.v23.78 kB30-04-08|11:58
syntax_decoding.v24.94 kB30-04-08|11:58
timescale.v546.00 B30-04-08|11:58
total_zeros_decoding.v14.96 kB30-04-08|11:58
vsim.wlf32.00 kB24-02-09|16:06
_primary.dat73.20 kB24-02-09|15:26
_primary.vhd11.00 kB24-02-09|15:26
verilog.asm49.59 kB21-02-09|17:50
_primary.dat7.28 kB21-02-09|17:50
_primary.vhd1.23 kB21-02-09|17:50
verilog.asm275.78 kB24-02-09|15:27
_primary.dat39.36 kB24-02-09|15:27
_primary.vhd4.99 kB24-02-09|15:27
_primary.dat15.08 kB26-02-09|11:49
_primary.vhd3.73 kB26-02-09|11:49
_primary.dat17.38 kB26-02-09|11:49
_primary.vhd4.65 kB26-02-09|11:49
verilog.asm61.01 kB22-02-09|21:56
_primary.dat8.81 kB19-02-09|20:59
_primary.vhd3.04 kB22-02-09|21:56
verilog.asm15.53 kB24-02-09|15:27
_primary.dat1.24 kB24-02-09|15:27
_primary.vhd902.00 B24-02-09|15:27
_primary.dat986.00 B26-02-09|11:49
_primary.vhd419.00 B26-02-09|11:49
_primary.dat1.40 kB26-02-09|11:49
_primary.vhd749.00 B26-02-09|11:49
_primary.dat328.00 B26-02-09|11:49
_primary.vhd307.00 B26-02-09|11:49
_primary.dat687.00 B26-02-09|11:49
_primary.vhd291.00 B26-02-09|11:49
_primary.dat1.73 kB26-02-09|11:24
_primary.vhd585.00 B26-02-09|11:24
_info2.66 kB26-02-09|11:49
syntmp0.00 B22-02-09|14:46
@inter_pred_reg_ctrl0.00 B24-02-09|15:26
@intra4x4_@pred@mode_decoding0.00 B21-02-09|17:50
@intra_pred_@p@e0.00 B24-02-09|15:27
@intra_pred_pipeline0.00 B26-02-09|11:49
@intra_pred_reg_ctrl0.00 B26-02-09|11:49
@intra_pred_top0.00 B22-02-09|21:56
@p@e0.00 B24-02-09|15:27
main_seed_precomputation0.00 B26-02-09|11:49
plane_@h@v_precomputation0.00 B26-02-09|11:49
plane_a_precomputation0.00 B26-02-09|11:49
plane_bc_precomputation0.00 B26-02-09|11:49
ram_sync_1r_sync_1w0.00 B26-02-09|11:24
_temp0.00 B26-02-09|11:49
rev_10.00 B22-02-09|14:06
work0.00 B26-02-09|11:49
H.2640.00 B08-03-09|19:18
...
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Sorry!This guy is mysterious, its blog hasn't been opened, try another, please!
OK

Warm tip!

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