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  • By lardiwas 2016-05-19
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			`timescale 1ns/10ps
`celldefine
module AND2X1 (A, B, Y);
input  A ;
input  B ;
output Y ;

   and (Y, A, B);

   specify
     // delay parameters
     specparam
       tpllh$A$Y = 0.34:0.34:0.34,
       tphhl$A$Y = 0.24:0.24:0.24,
       tpllh$B$Y = 0.34:0.34:0.34,
       tphhl$B$Y = 0.25:0.25:0.25;

     // path delays
     (A *> Y) = (tpllh$A$Y, tphhl$A$Y);
     (B *> Y) = (tpllh$B$Y, tphhl$B$Y);

   endspecify

endmodule
`endcelldefine

`timescale 1ns/10ps
`celldefine
module AND2X2 (A, B, Y);
input  A ;
input  B ;
output Y ;

   and (Y, A, B);

   specify
     // delay parameters
     specparam
       tpllh$A$Y = 0.062:0.062:0.062,
       tphhl$A$Y = 0.065:0.065:0.065,
       tpllh$B$Y = 0.062:0.062:0.062,
       tphhl$B$Y = 0.07:0.07:0.07;

     // path delays
     (A *> Y) = (tpllh$A$Y, tphhl$A$Y);
     (B *> Y) = (tpllh$B$Y, tphhl$B$Y);

   endspecify

endmodule
`endcelldefine

`timescale 1ns/10ps
`celldefine
module AOI21X1 (A, B, C, Y);
input  A ;
input  B ;
input  C ;
output Y ;

   and (I0_out, A, B);
   or  (I1_out, I0_out, C);
   not (Y, I1_out);

   specify
     // delay parameters
     specparam
       tplhl$A$Y = 0.2:0.2:0.2,
       tphlh$A$Y = 0.37:0.37:0.37,
       tplhl$B$Y = 0.2:0.2:0.2,
       tphlh$B$Y = 0.36:0.36:0.36,
       tplhl$C$Y = 0.23:0.23:0.23,
       tphlh$C$Y = 0.26:0.31:0.36;

     // path delays
     (A *> Y) = (tphlh$A$Y, tplhl$A$Y);
     (B *> Y) = (tphlh$B$Y, tplhl$B$Y);
     (C *> Y) = (tphlh$C$Y, tplhl$C$Y);

   endspecify

endmodule
`endcelldefine

`timescale 1ns/10ps
`celldefine
module AOI22X1 (C, D, Y, B, A);
input  C ;
input  D ;
input  B ;
input  A ;
output Y ;

   and (I0_out, C, D);
   and (I1_out, A, B);
   or  (I2_out, I0_out, I1_out);
   not (Y, I2_out);

   specify
     // delay parameters
     specparam
       tplhl$C$Y = 0.2:0.2:0.2,
       tphlh$C$Y = 0.27:0.32:0.37,
       tplhl$D$Y = 0.2:0.2:0.2,
       tphlh$D$Y = 0.27:0.32:0.37,
       tplhl$B$Y = 0.21:0.21:0.21,
       tphlh$B$Y = 0.3:0.34:0.38,
       tplhl$A$Y = 0.21:0.21:0.21,
       tphlh$A$Y = 0.3:0.34:0.38;

     // path delays
     (A *> Y) = (tphlh$A$Y, tplhl$A$Y);
     (B *> Y) = (tphlh$B$Y, tplhl$B$Y);
     (C *> Y) = (tphlh$C$Y, tplhl$C$Y);
     (D *> Y) = (tphlh$D$Y, tplhl$D$Y);

   endspecify

endmodule
`endcelldefine

`timescale 1ns/10ps
`celldefine
module BUFX2 (Y, A);
input  A ;
output Y ;

   buf (Y, A);

   specify
     // delay parameters
     specparam
       tpllh$A$Y = 0.064:0.064:0.064,
       tphhl$A$Y = 0.062:0.062:0.062;

     // path delays
     (A *> Y) = (tpllh$A$Y, tphhl$A$Y);

   endspecify

endmodule
`endcelldefine

`timescale 1ns/10ps
`celldefine
module BUFX4 (Y, A);
input  A ;
output Y ;

   buf (Y, A);

   specify
     // delay parameters
     specparam
       tpllh$A$Y = 0.048:0.048:0.048,
       tphhl$A$Y = 0.07:0.07:0.07;

     // path delays
     (A *> Y) = (tpllh$A$Y, tphhl$A$Y);

   endspecify

endmodule
`endcelldefine

`timescale 1ns/10ps
`celldefine
module CLKBUF1 (Y, A);
input  A ;
output Y ;

   buf (Y, A);

   specify
     // delay parameters
     specparam
       tpllh$A$Y = 0.12:0.12:0.12,
       tphhl$A$Y = 0.1:0.1:0.1;

     // path delays
     (A *> Y) = (tpllh$A$Y, tphhl$A$Y);

   endspecify

endmodule
`endcelldefine

`timescale 1ns/10ps
`celldefine
module CLKBUF2 (A, Y);
input  A ;
output Y ;

   buf (Y, A);

   specify
     // delay parameters
     specparam
       tpllh$A$Y = 0.14:0.14:0.14,
       tphhl$A$Y = 0.13:0.13:0.13;

     // path delays
     (A *> Y) = (tpllh$A$Y, tphhl$A$Y);

   endspecify

endmodule
`endcelldefine

`timescale 1ns/10ps
`celldefine
module CLKBUF3 (A, Y);
input  A ;
output Y ;

   buf (Y, A);

   specify
     // delay parameters
     specparam
       tpllh$A$Y = 0.17:0.17:0.17,
       tphhl$A$Y = 0.15:0.15:0.15;

     // path delays
     (A *> Y) = (tpllh$A$Y, tphhl$A$Y);

   endspecify

endmodule
`endcelldefine

`timescale 1ns/10ps
`celldefine
module DFFNEGX1 (Q, CLK, D);
input  CLK ;
input  D ;
output Q ;
reg NOTIFIER ;

   not (I0_CLOCK, CLK);
   udp_dff (DS0000, D, I0_CLOCK, 1'B0, 1'B0, NOTIFIER);
   not (P0000, DS0000);
   buf (Q, DS0000);

   specify
     // delay parameters
     specparam
       tphlh$CLK$Q = 0.22:0.22:0.22,
       tphhl$CLK$Q = 0.19:0.19:0.19,
       tminpwh$CLK = 0.021:0.04:0.06,
       tminpwl$CLK = 0.04:0.13:0.22,
       tsetup_negedge$D$CLK = 0.094:0.094:0.094,
       thold_negedge$D$CLK = 0:0:0,
       tsetup_posedge$D$CLK = 0.094:0.094:0.094,
       thold_posedge$D$CLK = -0.0000000022:-0.0000000022:-0.0000000022;

     // path delays
     if (CLK == 1'b0)
       (CLK *> Q) = (tphlh$CLK$Q, tphhl$CLK$Q);
     $setup(negedge D, negedge CLK, tsetup_negedge$D$CLK, NOTIFIER);
     $hold (negedge CLK, negedge D, thold_negedge$D$CLK,  NOTIFIER);
     $setup(posedge D, negedge CLK, tsetup_posedge$D$CLK, NOTIFIER);
     $hold (negedge CLK, posedge D, thold_posedge$D$CLK,  NOTIFIER);
     $width(posedge CLK, tminpwh$CLK, 0, NOTIFIER);
     $width(negedge CLK, tminpwl$CLK, 0, NOTIFIER);

   endspecify

endmodule
`endcelldefine

`timescale 1ns/10ps
`celldefine
module DFFPOSX1 (CLK, Q, D);
input  CLK ;
input  D ;
output Q ;
reg NOTIFIER ;

   udp_dff (DS0000, D, CLK, 1'B0, 1'B0, NOTIFIER);
   not (P0000, DS0000);
   buf (Q, DS0000);

   specify
     // delay parameters
     specparam
       tpllh$CLK$Q = 0.22:0.22:0.22,
       tplhl$CLK$Q = 0.2:0.2:0.2,
       tminpwh$CLK = 0.041:0.13:0.22,
       tminpwl$CLK = 0.042:0.055:0.069,
       tsetup_negedge$D$CLK = 0.094:0.094:0.094,
       thold_negedge$D$CLK = 0.0000000022:0.0000000022:0.0000000022,
       tsetup_posedge$D$CLK = 0.094:0.094:0.094,
       thold_posedge$D$CLK = 0:0:0;

     // path delays
     if (CLK == 1'b1)
       (CLK *> Q) = (tpllh$CLK$Q, tplhl$CLK$Q);
     $setup(negedge D, posedge CLK, tsetup_negedge$D$CLK, NOTIFIER);
     $hold (posedge CLK, negedge D, thold_negedge$D$CLK,  NOTIFIER);
     $setup(posedge D, posedge CLK, tsetup_posedge$D$CLK, NOTIFIER);
     $hold (posedge CLK, posedge D, thold_posedge$D$CLK,  NOTIFIER);
     $width(posedge CLK, tminpwh$CLK, 0, NOTIFIER);
     $width(negedge CLK, tminpwl$CLK, 0, NOTIFIER);

   endspecify

endmodule
`endcelldefine

`timescale 1ns/10ps
`celldefine
module DFFSR (CLK, D, S, R, Q);
input  CLK ;
input  D ;
input  S ;
input  R ;
output Q ;
reg NOTIFIER ;

   not (I0_CLEAR, R);
   not (I0_SET, S);
   udp_dff (P0003, D_, CLK, I0_SET, I0_CLEAR, NOTIFIER);
   not (D_, D);
   not (P0002, P0003);
   buf (Q, P0002);
   and (D_EQ_1_AN_S_EQ_1, D, S);
   not (I9_out, D);
   and (D_EQ_0_AN_R_EQ_1, I9_out, R);
   and (S_EQ_1_AN_R_EQ_1, S, R);

   specify
     // delay parameters
     specparam
       tpllh$CLK$Q = 0.43:0.43:0.43,
       tplhl$CLK$Q = 0.32:0.32:0.32,
       tphlh$S$Q = 0.4:0.4:0.4,
       tpllh$R$Q = 0.35:0.35:0.35,
       tphhl$R$Q = 0.26:0.26:0.26,
       tminpwh$CLK = 0.099:0.26:0.43,
       tminpwl$CLK = 0.11:0.13:0.14,
       tminpwl$S = 0.031:0.21:0.4,
       tminpwl$R = 0.022:0.14:0.26,
       tsetup_negedge$D$CLK = 0.094:0.094:0.094,
       thold_negedge$D$CLK = 0.0000000022:0.0000000022:0.0000000022,
       tsetup_posedge$D$CLK = 0.094:0.094:0.094,
       thold_posedge$D$CLK = 0:0:0,
       trec$R$CLK = 0:0:0,
       trem$R$CLK = 0.19:0.19:0.19,
       trec$R$S = 0:0:0,
       trec$S$CLK = 0:0:0,
       trem$S$CLK = 0.094:0.094:0.094,
       trec$S$R = 0.094:0.094:0.094;

     // path delays
     if (CLK == 1'b1)
       (CLK *> Q) = (tpllh$CLK$Q, tplhl$CLK$Q);
     (R *> Q) = (tpllh$R$Q, tphhl$R$Q);
     (S *> Q) = (tphlh$S$Q, 0);
     $setup(negedge D, posedge CLK &&& S_EQ_1_AN_R_EQ_1 == 1'b1, tsetup_negedge$D$CLK, NOTIFIER);
     $hold (posedge CLK &&& S_EQ_1_AN_R_EQ_1 == 1'b1, negedge D, thold_negedge$D$CLK,  NOTIFIER);
     $setup(posedge D, posedge CLK &&& S_EQ_1_AN_R_EQ_1 == 1'b1, tsetup_posedge$D$CLK, NOTIFIER);
     $hold (posedge CLK &&& S_EQ_1_AN_R_EQ_1 == 1'b1, posedge D, thold_posedge$D$CLK,  NOTIFIER);
     $recovery(posedge R, posedge CLK &&& D_EQ_1_AN_S_EQ_1 == 1'b1, trec$R$CLK, NOTIFIER);
     $removal (posedge R, posedge CLK &&& D_EQ_1_AN_S_EQ_1 == 1'b1, trem$R$CLK, NOTIFIER);
     $recovery(posedge R, posedge S, trec$R$S, NOTIFIER);
     $recovery(posedge S, posedge CLK &&& D_EQ_0_AN_R_EQ_1 == 1'b1, trec$S$CLK, NOTIFIER);
     $removal (posedge S, posedge CLK &&& D_EQ_0_AN_R_EQ_1 == 1'b1, trem$S$CLK, NOTIFIER);
     $recovery(posedge S, posedge R, trec$S$R, NOTIFIER);
     $width(posedge CLK, tminpwh$CLK, 0, NOTIFIER);
     $width(negedge CLK, tminpwl$CLK, 0, NOTIFIER);
     $width(negedge S, tminpwl$S, 0, NOTIFIER);
     $width(negedge R, tminpwl$R, 0, NOTIFIER);

   endspecify

endmodule
`endcelldefine

`timescale 1ns/10ps
`celldefine
module FAX1 (YC, B, C, A, YS);
input  B ;
input  C ;
input  A ;
output YC ;
output YS ;

   and (I0_out, A, B);
   and (I1_out, B, C);
   and (I3_out, C, A);
   or  (YC, I0_out, I1_out, I3_out);
   xor (I5_out, A, B);
   xor (YS, I5_out, C);

   specify
     // delay parameters
     specparam
       tpllh$B$YS = 0.35:0.38:0.41,
       tplhl$B$YS = 0.27:0.29:0.3,
       tpllh$B$YC = 0.36:0.36:0.37,
       tphhl$B$YC = 0.28:0.28:0.29,
       tpllh$C$YS = 0.35:0.37:0.4,
       tplhl$C$YS = 0.28:0.28:0.29,
       tpllh$C$YC = 0.35:0.36:0.36,
       tphhl$C$YC = 0.27:0.28:0.28,
       tpllh$A$YS = 0.36:0.39:0.41,
       tplhl$A$YS = 0.28:0.29:0.3,
       tpllh$A$YC = 0.36:0.36:0.36,
       tphhl$A$YC = 0.28:0.28:0.28;

     // path delays
     (A *> YC) = (tpllh$A$YC, tphhl$A$YC);
     (A *> YS) = (tpllh$A$YS, tplhl$A$YS);
     (B *> YC) = (tpllh$B$YC, tphhl$B$YC);
     (B *> YS) = (tpllh$B$YS, tplhl$B$YS);
     (C *> YC) = (tpllh$C$YC, tphhl$C$YC);
     (C *> YS) = (tpllh$C$YS, tplhl$C$YS);

   endspecify

endmodule
`endcelldefine

`timescale 1ns/10ps
`celldefine
module HAX1 (YS, B, A, YC);
input  B ;
input  A ;
output YS ;
output YC ;

   xor (YS, A, B);
   and (YC, A, B);

   specify
     // delay parameters
     specparam
       tpllh$B$YS = 0.34:0.36:0.37,
       tplhl$B$YS = 0.25:0.26:0.27,
       tpllh$B$YC = 0.35:0.35:0.35,
       tphhl$B$YC = 0.26:0.26:0.26,
       tpllh$A$YS = 0.35:0.36:0.38,
       tplhl$A$YS = 0.26:0.26:0.27,
       tpllh$A$YC = 0.34:0.34:0.34,
       tphhl$A$YC = 0.26:0.26:0.26;

     // path delays
     (A *> YC) = (tpllh$A$YC, tphhl$A$YC);
 
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OR2X1.dmp2.06 kB25-04-16|01:43
OR2X1.recent2.00 B25-04-16|01:43
OR2X2.dmp2.09 kB25-04-16|01:43
OR2X2.recent2.00 B25-04-16|01:43
TBUFX1.dmp2.64 kB25-04-16|01:43
TBUFX1.recent2.00 B25-04-16|01:43
TBUFX2.dmp2.67 kB25-04-16|01:43
TBUFX2.recent2.00 B25-04-16|01:43
udp_dff.dmp3.42 kB25-04-16|01:43
udp_mux2.dmp1.79 kB25-04-16|01:43
udp_rslat.dmp1.87 kB25-04-16|01:43
udp_tlat.dmp3.30 kB25-04-16|01:43
XNOR2X1.dmp2.31 kB25-04-16|01:43
XNOR2X1.recent2.00 B25-04-16|01:43
XOR2X1.dmp2.15 kB25-04-16|01:43
XOR2X1.recent2.00 B25-04-16|01:43
adder.dmp2.29 kB25-04-16|01:44
adder.recent2.00 B25-04-16|01:44
adder_32.dmp15.57 kB25-04-16|01:44
adder_32.recent2.00 B25-04-16|01:44
addsub_32.dmp9.90 kB25-04-16|01:44
addsub_32.recent2.00 B25-04-16|01:44
alu_32.dmp5.42 kB25-04-16|01:44
alu_32.recent2.00 B25-04-16|01:44
and_32.dmp1.29 kB25-04-16|01:44
and_32.recent2.00 B25-04-16|01:44
compare_32.dmp1.24 kB25-04-16|01:44
compare_32.recent2.00 B25-04-16|01:44
control.dmp7.91 kB25-04-16|01:44
control.recent2.00 B25-04-16|01:44
cpu32.dmp8.55 kB25-04-16|01:44
cpu32.recent2.00 B25-04-16|01:44
decoder2to4.dmp2.25 kB25-04-16|01:44
decoder2to4.recent2.00 B25-04-16|01:44
decoder3to8.dmp1.85 kB25-04-16|01:44
decoder3to8.recent2.00 B25-04-16|01:44
decoder4to16.dmp1.88 kB25-04-16|01:44
decoder4to16.recent2.00 B25-04-16|01:44
dff.dmp987.00 B25-04-16|01:44
dff.recent2.00 B25-04-16|01:44
dff_32.dmp8.89 kB25-04-16|01:44
dff_32.recent2.00 B25-04-16|01:44
dff_8.dmp2.85 kB25-04-16|01:44
dff_8.recent2.00 B25-04-16|01:44
inc_8.dmp4.13 kB25-04-16|01:44
inc_8.recent2.00 B25-04-16|01:44
memory16_32.dmp10.36 kB25-04-16|01:44
memory16_32.recent2.00 B25-04-16|01:44
memory_32.dmp2.69 kB25-04-16|01:44
memory_32.recent2.00 B25-04-16|01:44
mux2to1.dmp1.73 kB25-04-16|01:44
mux2to1.recent2.00 B25-04-16|01:44
mux2to1_32.dmp11.82 kB25-04-16|01:44
mux2to1_32.recent2.00 B25-04-16|01:44
mux2to1_8.dmp3.82 kB25-04-16|01:44
mux2to1_8.recent2.00 B25-04-16|01:44
PC.dmp3.50 kB25-04-16|01:44
PC.recent2.00 B25-04-16|01:44
shift_left_logic_32.dmp4.57 kB25-04-16|01:44
shift_left_logic_32.recent2.00 B25-04-16|01:44
shift_right_logic_32.dmp4.61 kB25-04-16|01:44
shift_right_logic_32.recent2.00 B25-04-16|01:44
tris.dmp927.00 B25-04-16|01:44
tris.recent2.00 B25-04-16|01:44
tris_32.dmp8.15 kB25-04-16|01:44
tris_32.recent2.00 B25-04-16|01:44
xnor_32.dmp1.33 kB25-04-16|01:44
xnor_32.recent2.00 B25-04-16|01:44
_license_string23.00 B24-04-16|20:36
GTECH_COMPONENTS.dep347.00 B25-04-16|02:05
GTECH_COMPONENTS.dmp21.61 kB25-04-16|02:05
GTECH_COMPONENTS.dep117.00 B25-04-16|02:05
GTECH_COMPONENTS.dmp1.68 kB25-04-16|02:05
AND2X1.dmp1.49 kB25-04-16|02:10
AND2X1.recent2.00 B25-04-16|02:10
AND2X2.dmp1.52 kB25-04-16|02:10
AND2X2.recent2.00 B25-04-16|02:10
AOI21X1.dmp2.40 kB25-04-16|02:10
AOI21X1.recent2.00 B25-04-16|02:10
AOI22X1.dmp3.12 kB25-04-16|02:10
AOI22X1.recent2.00 B25-04-16|02:10
BUFX2.dmp1.10 kB25-04-16|02:10
BUFX2.recent2.00 B25-04-16|02:10
BUFX4.dmp1.14 kB25-04-16|02:10
BUFX4.recent2.00 B25-04-16|02:10
CLKBUF1.dmp1.15 kB25-04-16|02:10
CLKBUF1.recent2.00 B25-04-16|02:10
CLKBUF2.dmp1.17 kB25-04-16|02:10
CLKBUF2.recent2.00 B25-04-16|02:10
CLKBUF3.dmp1.18 kB25-04-16|02:10
CLKBUF3.recent2.00 B25-04-16|02:10
DFFNEGX1.dmp4.21 kB25-04-16|02:10
DFFNEGX1.recent2.00 B25-04-16|02:10
DFFPOSX1.dmp3.99 kB25-04-16|02:10
DFFPOSX1.recent2.00 B25-04-16|02:10
DFFSR.dmp9.35 kB25-04-16|02:10
DFFSR.recent2.00 B25-04-16|02:10
FAX1.dmp4.82 kB25-04-16|02:10
FAX1.recent2.00 B25-04-16|02:10
HAX1.dmp2.94 kB25-04-16|02:10
HAX1.recent2.00 B25-04-16|02:10
INVX1.dmp1.27 kB25-04-16|02:10
INVX1.recent2.00 B25-04-16|02:10
INVX2.dmp1.30 kB25-04-16|02:10
INVX2.recent2.00 B25-04-16|02:10
INVX4.dmp1.31 kB25-04-16|02:10
INVX4.recent2.00 B25-04-16|02:10
INVX8.dmp1.33 kB25-04-16|02:10
INVX8.recent2.00 B25-04-16|02:10
LATCH.dmp4.26 kB25-04-16|02:10
LATCH.recent2.00 B25-04-16|02:10
MUX2X1.dmp2.71 kB25-04-16|02:10
MUX2X1.recent2.00 B25-04-16|02:10
NAND2X1.dmp2.13 kB25-04-16|02:10
NAND2X1.recent2.00 B25-04-16|02:10
NAND3X1.dmp2.74 kB25-04-16|02:10
NAND3X1.recent2.00 B25-04-16|02:10
NOR2X1.dmp2.18 kB25-04-16|02:10
NOR2X1.recent2.00 B25-04-16|02:10
NOR3X1.dmp2.78 kB25-04-16|02:10
NOR3X1.recent2.00 B25-04-16|02:10
OAI21X1.dmp2.97 kB25-04-16|02:10
OAI21X1.recent2.00 B25-04-16|02:10
OAI22X1.dmp3.76 kB25-04-16|02:10
OAI22X1.recent2.00 B25-04-16|02:10
OR2X1.dmp2.06 kB25-04-16|02:10
OR2X1.recent2.00 B25-04-16|02:10
OR2X2.dmp2.09 kB25-04-16|02:10
OR2X2.recent2.00 B25-04-16|02:10
TBUFX1.dmp2.64 kB25-04-16|02:10
TBUFX1.recent2.00 B25-04-16|02:10
TBUFX2.dmp2.67 kB25-04-16|02:10
TBUFX2.recent2.00 B25-04-16|02:10
udp_dff.dmp3.42 kB25-04-16|02:10
udp_mux2.dmp1.79 kB25-04-16|02:10
udp_rslat.dmp1.87 kB25-04-16|02:10
udp_tlat.dmp3.30 kB25-04-16|02:10
XNOR2X1.dmp2.31 kB25-04-16|02:10
XNOR2X1.recent2.00 B25-04-16|02:10
XOR2X1.dmp2.15 kB25-04-16|02:10
XOR2X1.recent2.00 B25-04-16|02:10
adder.dmp2.29 kB25-04-16|02:06
adder.recent2.00 B25-04-16|02:06
adder_32.dmp15.57 kB25-04-16|02:06
adder_32.recent2.00 B25-04-16|02:06
addsub_32.dmp9.90 kB25-04-16|02:06
addsub_32.recent2.00 B25-04-16|02:06
alu_32.dmp5.42 kB25-04-16|02:06
alu_32.recent2.00 B25-04-16|02:06
and_32.dmp1.29 kB25-04-16|02:06
and_32.recent2.00 B25-04-16|02:06
compare_32.dmp1.24 kB25-04-16|02:06
compare_32.recent2.00 B25-04-16|02:06
control.dmp7.91 kB25-04-16|02:06
control.recent2.00 B25-04-16|02:06
cpu32.dmp8.55 kB25-04-16|02:06
cpu32.recent2.00 B25-04-16|02:06
decoder2to4.dmp2.25 kB25-04-16|02:06
decoder2to4.recent2.00 B25-04-16|02:06
decoder3to8.dmp1.85 kB25-04-16|02:06
decoder3to8.recent2.00 B25-04-16|02:06
decoder4to16.dmp1.88 kB25-04-16|02:06
decoder4to16.recent2.00 B25-04-16|02:06
dff.dmp987.00 B25-04-16|02:06
dff.recent2.00 B25-04-16|02:06
dff_32.dmp8.89 kB25-04-16|02:06
dff_32.recent2.00 B25-04-16|02:06
dff_8.dmp2.85 kB25-04-16|02:06
dff_8.recent2.00 B25-04-16|02:06
inc_8.dmp4.13 kB25-04-16|02:06
inc_8.recent2.00 B25-04-16|02:06
memory16_32.dmp10.36 kB25-04-16|02:06
memory16_32.recent2.00 B25-04-16|02:06
memory_32.dmp2.69 kB25-04-16|02:06
memory_32.recent2.00 B25-04-16|02:06
mux2to1.dmp1.73 kB25-04-16|02:06
mux2to1.recent2.00 B25-04-16|02:06
mux2to1_32.dmp11.82 kB25-04-16|02:06
mux2to1_32.recent2.00 B25-04-16|02:06
mux2to1_8.dmp3.82 kB25-04-16|02:06
mux2to1_8.recent2.00 B25-04-16|02:06
PC.dmp3.50 kB25-04-16|02:06
PC.recent2.00 B25-04-16|02:06
shift_left_logic_32.dmp4.57 kB25-04-16|02:06
shift_left_logic_32.recent2.00 B25-04-16|02:06
shift_right_logic_32.dmp4.61 kB25-04-16|02:06
shift_right_logic_32.recent2.00 B25-04-16|02:06
tris.dmp927.00 B25-04-16|02:06
tris.recent2.00 B25-04-16|02:06
tris_32.dmp8.15 kB25-04-16|02:06
tris_32.recent2.00 B25-04-16|02:06
xnor_32.dmp1.33 kB25-04-16|02:06
xnor_32.recent2.00 B25-04-16|02:06
_license_string23.00 B25-04-16|02:05
GTECH_COMPONENTS.dep347.00 B25-04-16|05:37
GTECH_COMPONENTS.dmp21.61 kB25-04-16|05:37
GTECH_COMPONENTS.dep117.00 B25-04-16|05:37
GTECH_COMPONENTS.dmp1.68 kB25-04-16|05:37
AND2X1.dmp1.49 kB25-04-16|05:38
AND2X1.recent2.00 B25-04-16|05:38
AND2X2.dmp1.52 kB25-04-16|05:38
AND2X2.recent2.00 B25-04-16|05:38
AOI21X1.dmp2.40 kB25-04-16|05:38
AOI21X1.recent2.00 B25-04-16|05:38
AOI22X1.dmp3.12 kB25-04-16|05:38
AOI22X1.recent2.00 B25-04-16|05:38
BUFX2.dmp1.10 kB25-04-16|05:38
BUFX2.recent2.00 B25-04-16|05:38
BUFX4.dmp1.14 kB25-04-16|05:38
BUFX4.recent2.00 B25-04-16|05:38
CLKBUF1.dmp1.15 kB25-04-16|05:38
CLKBUF1.recent2.00 B25-04-16|05:38
CLKBUF2.dmp1.17 kB25-04-16|05:38
CLKBUF2.recent2.00 B25-04-16|05:38
CLKBUF3.dmp1.18 kB25-04-16|05:38
CLKBUF3.recent2.00 B25-04-16|05:38
DFFNEGX1.dmp4.21 kB25-04-16|05:38
DFFNEGX1.recent2.00 B25-04-16|05:38
DFFPOSX1.dmp3.99 kB25-04-16|05:38
DFFPOSX1.recent2.00 B25-04-16|05:38
DFFSR.dmp9.35 kB25-04-16|05:38
DFFSR.recent2.00 B25-04-16|05:38
FAX1.dmp4.82 kB25-04-16|05:38
FAX1.recent2.00 B25-04-16|05:38
HAX1.dmp2.94 kB25-04-16|05:38
HAX1.recent2.00 B25-04-16|05:38
INVX1.dmp1.27 kB25-04-16|05:38
INVX1.recent2.00 B25-04-16|05:38
INVX2.dmp1.30 kB25-04-16|05:38
INVX2.recent2.00 B25-04-16|05:38
INVX4.dmp1.31 kB25-04-16|05:38
INVX4.recent2.00 B25-04-16|05:38
INVX8.dmp1.33 kB25-04-16|05:38
INVX8.recent2.00 B25-04-16|05:38
LATCH.dmp4.26 kB25-04-16|05:38
LATCH.recent2.00 B25-04-16|05:38
MUX2X1.dmp2.71 kB25-04-16|05:38
MUX2X1.recent2.00 B25-04-16|05:38
NAND2X1.dmp2.13 kB25-04-16|05:38
NAND2X1.recent2.00 B25-04-16|05:38
NAND3X1.dmp2.74 kB25-04-16|05:38
NAND3X1.recent2.00 B25-04-16|05:38
NOR2X1.dmp2.18 kB25-04-16|05:38
NOR2X1.recent2.00 B25-04-16|05:38
NOR3X1.dmp2.78 kB25-04-16|05:38
NOR3X1.recent2.00 B25-04-16|05:38
OAI21X1.dmp2.97 kB25-04-16|05:38
OAI21X1.recent2.00 B25-04-16|05:38
OAI22X1.dmp3.76 kB25-04-16|05:38
OAI22X1.recent2.00 B25-04-16|05:38
OR2X1.dmp2.06 kB25-04-16|05:38
OR2X1.recent2.00 B25-04-16|05:38
OR2X2.dmp2.09 kB25-04-16|05:38
OR2X2.recent2.00 B25-04-16|05:38
TBUFX1.dmp2.64 kB25-04-16|05:38
TBUFX1.recent2.00 B25-04-16|05:38
TBUFX2.dmp2.67 kB25-04-16|05:38
TBUFX2.recent2.00 B25-04-16|05:38
udp_dff.dmp3.42 kB25-04-16|05:38
udp_mux2.dmp1.79 kB25-04-16|05:38
udp_rslat.dmp1.87 kB25-04-16|05:38
udp_tlat.dmp3.30 kB25-04-16|05:38
XNOR2X1.dmp2.31 kB25-04-16|05:38
XNOR2X1.recent2.00 B25-04-16|05:38
XOR2X1.dmp2.15 kB25-04-16|05:38
XOR2X1.recent2.00 B25-04-16|05:38
adder.dmp2.29 kB25-04-16|05:37
adder.recent2.00 B25-04-16|05:37
adder_32.dmp15.57 kB25-04-16|05:37
adder_32.recent2.00 B25-04-16|05:37
addsub_32.dmp9.90 kB25-04-16|05:37
addsub_32.recent2.00 B25-04-16|05:37
alu_32.dmp5.42 kB25-04-16|05:37
alu_32.recent2.00 B25-04-16|05:37
and_32.dmp1.29 kB25-04-16|05:37
and_32.recent2.00 B25-04-16|05:37
compare_32.dmp1.24 kB25-04-16|05:37
compare_32.recent2.00 B25-04-16|05:37
control.dmp7.91 kB25-04-16|05:37
control.recent2.00 B25-04-16|05:37
cpu32.dmp8.55 kB25-04-16|05:37
cpu32.recent2.00 B25-04-16|05:37
decoder2to4.dmp2.25 kB25-04-16|05:37
decoder2to4.recent2.00 B25-04-16|05:37
decoder3to8.dmp1.85 kB25-04-16|05:37
decoder3to8.recent2.00 B25-04-16|05:37
decoder4to16.dmp1.88 kB25-04-16|05:37
decoder4to16.recent2.00 B25-04-16|05:37
dff.dmp987.00 B25-04-16|05:37
dff.recent2.00 B25-04-16|05:37
dff_32.dmp8.89 kB25-04-16|05:37
dff_32.recent2.00 B25-04-16|05:37
dff_8.dmp2.85 kB25-04-16|05:37
dff_8.recent2.00 B25-04-16|05:37
inc_8.dmp4.13 kB25-04-16|05:37
inc_8.recent2.00 B25-04-16|05:37
memory16_32.dmp10.36 kB25-04-16|05:37
memory16_32.recent2.00 B25-04-16|05:37
memory_32.dmp2.69 kB25-04-16|05:37
memory_32.recent2.00 B25-04-16|05:37
mux2to1.dmp1.73 kB25-04-16|05:37
mux2to1.recent2.00 B25-04-16|05:37
mux2to1_32.dmp11.82 kB25-04-16|05:37
mux2to1_32.recent2.00 B25-04-16|05:37
mux2to1_8.dmp3.82 kB25-04-16|05:37
mux2to1_8.recent2.00 B25-04-16|05:37
PC.dmp3.50 kB25-04-16|05:37
PC.recent2.00 B25-04-16|05:37
shift_left_logic_32.dmp4.57 kB25-04-16|05:37
shift_left_logic_32.recent2.00 B25-04-16|05:37
shift_right_logic_32.dmp4.61 kB25-04-16|05:37
shift_right_logic_32.recent2.00 B25-04-16|05:37
tris.dmp927.00 B25-04-16|05:37
tris.recent2.00 B25-04-16|05:37
tris_32.dmp8.15 kB25-04-16|05:37
tris_32.recent2.00 B25-04-16|05:37
xnor_32.dmp1.33 kB25-04-16|05:37
xnor_32.recent2.00 B25-04-16|05:37
_license_string24.00 B25-04-16|05:37
formality.lck0.00 B24-04-16|19:04
formality.log0.00 B24-04-16|19:04
formality1.lck0.00 B24-04-16|20:36
formality1.log49.08 kB25-04-16|01:46
formality2.lck0.00 B25-04-16|02:05
formality2.log16.67 kB25-04-16|02:11
formality3.lck0.00 B25-04-16|05:37
formality3.log16.67 kB25-04-16|05:38
formality4.log13.72 kB25-04-16|06:09
gds2_encounter.map2.08 kB07-04-16|14:58
gds2_virtuoso.map1.20 kB07-04-16|14:58
gscl45nm.v21.99 kB07-04-16|14:58
ipo1.txt356.00 B25-04-16|06:06
ipo2.txt356.00 B25-04-16|06:07
power.final3.92 kB25-04-16|06:08
power.rep2.14 kB27-04-16|12:45
report.ctsmdl101.00 B25-04-16|06:07
report.ctsrpt44.20 kB25-04-16|06:07
report.post_troute.ctsrpt44.21 kB25-04-16|06:07
shm.dsn516.55 kB27-04-16|12:43
shm.trn1.79 MB27-04-16|12:43
skew.post_troute_local.ctsrpt44.39 kB25-04-16|06:07
timing.rep7.00 kB27-04-16|12:45
timing.rep.1.placed184.59 kB25-04-16|06:06
timing.rep.2.ipo1184.59 kB25-04-16|06:06
timing.rep.3.cts184.61 kB25-04-16|06:07
timing.rep.4.ipo2172.02 kB25-04-16|06:07
timing.rep.5.final172.02 kB25-04-16|06:08
verilog.log14.66 kB27-04-16|12:43
adder-verilog.pvl2.62 kB27-04-16|12:44
adder-verilog.syn280.00 B27-04-16|12:44
ADDER.mr23.00 B27-04-16|12:44
adder_32-verilog.pvl12.80 kB27-04-16|12:44
adder_32-verilog.syn285.00 B27-04-16|12:44
ADDER_32.mr23.00 B27-04-16|12:44
addsub_32-verilog.pvl7.85 kB27-04-16|12:44
addsub_32-verilog.syn284.00 B27-04-16|12:44
ADDSUB_32.mr23.00 B27-04-16|12:44
alu_32-verilog.pvl4.99 kB27-04-16|12:44
alu_32-verilog.syn283.00 B27-04-16|12:44
ALU_32.mr23.00 B27-04-16|12:44
and_32-verilog.pvl1.72 kB27-04-16|12:44
and_32-verilog.syn281.00 B27-04-16|12:44
AND_32.mr23.00 B27-04-16|12:44
compare_32-verilog.pvl1.59 kB25-04-16|02:17
compare_32-verilog.syn287.00 B25-04-16|02:17
COMPARE_32.mr23.00 B25-04-16|02:17
control-verilog.pvl5.92 kB27-04-16|12:44
control-verilog.syn284.00 B27-04-16|12:44
CONTROL.mr23.00 B27-04-16|12:44
cpu32-verilog.pvl6.95 kB27-04-16|12:44
cpu32-verilog.syn280.00 B27-04-16|12:44
CPU32.mr23.00 B27-04-16|12:44
decoder2to4-verilog.pvl2.71 kB27-04-16|12:44
decoder2to4-verilog.syn288.00 B27-04-16|12:44
DECODER2TO4.mr23.00 B27-04-16|12:44
decoder3to8-verilog.pvl2.61 kB27-04-16|12:44
decoder3to8-verilog.syn288.00 B27-04-16|12:44
DECODER3TO8.mr23.00 B27-04-16|12:44
decoder4to16-verilog.pvl2.61 kB27-04-16|12:44
decoder4to16-verilog.syn289.00 B27-04-16|12:44
DECODER4TO16.mr23.00 B27-04-16|12:44
dff-verilog.pvl1.54 kB27-04-16|12:44
dff-verilog.syn280.00 B27-04-16|12:44
DFF.mr23.00 B27-04-16|12:44
dff_32-verilog.pvl7.40 kB27-04-16|12:44
dff_32-verilog.syn283.00 B27-04-16|12:44
DFF_32.mr23.00 B27-04-16|12:44
dff_8-verilog.pvl2.94 kB27-04-16|12:44
dff_8-verilog.syn280.00 B27-04-16|12:44
DFF_8.mr23.00 B27-04-16|12:44
inc_8-verilog.pvl4.02 kB27-04-16|12:44
inc_8-verilog.syn282.00 B27-04-16|12:44
INC_8.mr23.00 B27-04-16|12:44
memory16_32-verilog.pvl7.35 kB27-04-16|12:44
memory16_32-verilog.syn288.00 B27-04-16|12:44
MEMORY16_32.mr23.00 B27-04-16|12:44
memory_32-verilog.pvl2.88 kB27-04-16|12:44
memory_32-verilog.syn286.00 B27-04-16|12:44
MEMORY_32.mr23.00 B27-04-16|12:44
mux2to1-verilog.pvl2.33 kB27-04-16|12:44
mux2to1-verilog.syn282.00 B27-04-16|12:44
MUX2TO1.mr23.00 B27-04-16|12:44
mux2to1_32-verilog.pvl8.80 kB27-04-16|12:44
mux2to1_32-verilog.syn287.00 B27-04-16|12:44
MUX2TO1_32.mr23.00 B27-04-16|12:44
mux2to1_8-verilog.pvl3.35 kB27-04-16|12:44
mux2to1_8-verilog.syn286.00 B27-04-16|12:44
MUX2TO1_8.mr23.00 B27-04-16|12:44
PC-verilog.pvl3.37 kB27-04-16|12:44
PC-verilog.syn277.00 B27-04-16|12:44
PC.mr23.00 B27-04-16|12:44
shift_left_logic_32-verilog.pvl4.17 kB27-04-16|12:44
shift_left_logic_32-verilog.syn296.00 B27-04-16|12:44
SHIFT_LEFT_LOGIC_32.mr23.00 B27-04-16|12:44
shift_right_logic_32-verilog.pvl4.17 kB27-04-16|12:44
shift_right_logic_32-verilog.syn297.00 B27-04-16|12:44
SHIFT_RIGHT_LOGIC_32.mr23.00 B27-04-16|12:44
tris-verilog.pvl1.60 kB27-04-16|12:44
tris-verilog.syn281.00 B27-04-16|12:44
TRIS.mr23.00 B27-04-16|12:44
tris_32-verilog.pvl7.41 kB27-04-16|12:44
tris_32-verilog.syn282.00 B27-04-16|12:44
TRIS_32.mr23.00 B27-04-16|12:44
xnor_32-verilog.pvl1.73 kB27-04-16|12:44
xnor_32-verilog.syn284.00 B27-04-16|12:44
XNOR_32.mr23.00 B27-04-16|12:44
.routing_guide.rgf28.08 kB25-04-16|13:23
.tmp.cfp4.50 kB25-04-16|13:23
area.final131.00 B25-04-16|13:24
cell.rep340.80 kB25-04-16|14:40
code.hex181.00 B23-04-16|19:08
command.log174.10 kB25-04-16|14:40
compile_dc.tcl2.59 kB25-04-16|13:08
compile_dc.tcl~2.59 kB25-04-16|13:00
cpu32.conn.rpt496.00 B25-04-16|13:24
cpu32.cts_trace17.43 kB25-04-16|13:23
cpu32.geom.rpt527.00 B25-04-16|13:24
cpu32.sdc5.06 kB25-04-16|14:40
cpu32.v17.67 kB23-04-16|19:29
cpu32.vh451.10 kB25-04-16|14:40
cpu32_modify.v~15.29 kB27-04-16|10:44
cpu32_test.v2.04 kB19-04-16|22:38
cts.rguide0.00 B25-04-16|13:23
CTS_RP_MOVE.txt346.00 B25-04-16|13:23
default.svf56.75 kB25-04-16|14:40
encounter.cmd822.00 B25-04-16|13:04
encounter.cmd12.91 kB25-04-16|13:25
encounter.conf2.71 kB25-04-16|13:11
encounter.conf~2.71 kB25-04-16|13:04
encounter.cts1.56 kB25-04-16|13:23
encounter.log3.90 kB25-04-16|13:04
encounter.log1120.65 kB25-04-16|13:25
encounter.tcl3.66 kB07-04-16|14:58
encounter.tcl.old_jan20143.47 kB07-04-16|14:58
final.dspf10.82 MB25-04-16|13:24
final.gds24.20 MB25-04-16|13:24
final.v480.75 kB25-04-16|13:24
fm_shell_command.log1.84 kB25-04-16|13:27
formality.log13.71 kB25-04-16|13:26
gds2_encounter.map2.08 kB07-04-16|14:58
gds2_virtuoso.map1.20 kB07-04-16|14:58
gscl45nm.v21.99 kB07-04-16|14:58
ipo1.txt356.00 B25-04-16|13:23
ipo2.txt356.00 B25-04-16|13:24
libManager.log813.00 B25-04-16|13:29
power.final3.92 kB25-04-16|13:24
power.rep2.14 kB25-04-16|14:40
report.ctsmdl101.00 B25-04-16|13:23
report.ctsrpt44.45 kB25-04-16|13:23
report.post_troute.ctsrpt44.36 kB25-04-16|13:23
shm.dsn521.70 kB27-04-16|11:41
shm.trn1.86 MB27-04-16|11:41
skew.post_troute_local.ctsrpt44.54 kB25-04-16|13:23
timing.rep7.30 kB25-04-16|14:40
timing.rep.1.placed232.14 kB25-04-16|13:23
timing.rep.2.ipo1232.14 kB25-04-16|13:23
timing.rep.3.cts231.92 kB25-04-16|13:24
timing.rep.4.ipo2180.75 kB25-04-16|13:24
timing.rep.5.final181.26 kB25-04-16|13:24
verilog.log14.66 kB27-04-16|11:41
adder-verilog.pvl2.62 kB25-04-16|14:38
adder-verilog.syn280.00 B25-04-16|14:38
ADDER.mr23.00 B25-04-16|14:38
adder1-verilog.pvl2.85 kB25-04-16|14:38
adder1-verilog.syn283.00 B25-04-16|14:38
ADDER1.mr23.00 B25-04-16|14:38
adder4-verilog.pvl3.63 kB25-04-16|14:38
adder4-verilog.syn281.00 B25-04-16|14:38
ADDER4.mr23.00 B25-04-16|14:38
adder_32-verilog.pvl4.73 kB25-04-16|14:38
adder_32-verilog.syn285.00 B25-04-16|14:38
ADDER_32.mr23.00 B25-04-16|14:38
addsub_32-verilog.pvl7.86 kB25-04-16|14:38
addsub_32-verilog.syn286.00 B25-04-16|14:38
ADDSUB_32.mr23.00 B25-04-16|14:38
alu_32-verilog.pvl4.99 kB25-04-16|14:38
alu_32-verilog.syn283.00 B25-04-16|14:38
ALU_32.mr23.00 B25-04-16|14:38
and_32-verilog.pvl1.72 kB25-04-16|14:38
and_32-verilog.syn281.00 B25-04-16|14:38
AND_32.mr23.00 B25-04-16|14:38
control-verilog.pvl5.92 kB25-04-16|14:38
control-verilog.syn284.00 B25-04-16|14:38
CONTROL.mr23.00 B25-04-16|14:38
cpu32-verilog.pvl6.95 kB25-04-16|14:38
cpu32-verilog.syn280.00 B25-04-16|14:38
CPU32.mr23.00 B25-04-16|14:38
decoder2to4-verilog.pvl2.71 kB25-04-16|14:38
decoder2to4-verilog.syn288.00 B25-04-16|14:38
DECODER2TO4.mr23.00 B25-04-16|14:38
decoder3to8-verilog.pvl2.61 kB25-04-16|14:38
decoder3to8-verilog.syn288.00 B25-04-16|14:38
DECODER3TO8.mr23.00 B25-04-16|14:38
decoder4to16-verilog.pvl2.61 kB25-04-16|14:38
decoder4to16-verilog.syn289.00 B25-04-16|14:38
DECODER4TO16.mr23.00 B25-04-16|14:38
dff-verilog.pvl1.54 kB25-04-16|14:38
dff-verilog.syn280.00 B25-04-16|14:38
DFF.mr23.00 B25-04-16|14:38
dff_32-verilog.pvl7.40 kB25-04-16|14:38
dff_32-verilog.syn283.00 B25-04-16|14:38
DFF_32.mr23.00 B25-04-16|14:38
dff_8-verilog.pvl2.94 kB25-04-16|14:38
dff_8-verilog.syn280.00 B25-04-16|14:38
DFF_8.mr23.00 B25-04-16|14:38
inc_8-verilog.pvl4.02 kB25-04-16|14:38
inc_8-verilog.syn282.00 B25-04-16|14:38
INC_8.mr23.00 B25-04-16|14:38
memory16_32-verilog.pvl7.35 kB25-04-16|14:38
memory16_32-verilog.syn288.00 B25-04-16|14:38
MEMORY16_32.mr23.00 B25-04-16|14:38
memory_32-verilog.pvl2.88 kB25-04-16|14:38
memory_32-verilog.syn286.00 B25-04-16|14:38
MEMORY_32.mr23.00 B25-04-16|14:38
mux2to1-verilog.pvl2.33 kB25-04-16|14:38
mux2to1-verilog.syn282.00 B25-04-16|14:38
MUX2TO1.mr23.00 B25-04-16|14:38
mux2to1_32-verilog.pvl8.80 kB25-04-16|14:38
mux2to1_32-verilog.syn287.00 B25-04-16|14:38
MUX2TO1_32.mr23.00 B25-04-16|14:38
mux2to1_8-verilog.pvl3.35 kB25-04-16|14:38
mux2to1_8-verilog.syn286.00 B25-04-16|14:38
MUX2TO1_8.mr23.00 B25-04-16|14:38
PC-verilog.pvl3.37 kB25-04-16|14:38
PC-verilog.syn277.00 B25-04-16|14:38
PC.mr23.00 B25-04-16|14:38
shift_left_logic_32-verilog.pvl4.17 kB25-04-16|14:38
shift_left_logic_32-verilog.syn296.00 B25-04-16|14:38
SHIFT_LEFT_LOGIC_32.mr23.00 B25-04-16|14:38
shift_right_logic_32-verilog.pvl4.17 kB25-04-16|14:38
shift_right_logic_32-verilog.syn295.00 B25-04-16|14:38
SHIFT_RIGHT_LOGIC_32.mr23.00 B25-04-16|14:38
tris-verilog.pvl1.60 kB25-04-16|14:38
tris-verilog.syn281.00 B25-04-16|14:38
TRIS.mr23.00 B25-04-16|14:38
tris_32-verilog.pvl7.41 kB25-04-16|14:38
tris_32-verilog.syn282.00 B25-04-16|14:38
TRIS_32.mr23.00 B25-04-16|14:38
xnor_32-verilog.pvl1.73 kB25-04-16|14:38
xnor_32-verilog.syn284.00 B25-04-16|14:38
XNOR_32.mr23.00 B25-04-16|14:38
GTECH_COMPONENTS.pbd0.00 B28-04-16|14:14
GTECH_COMPONENTS.pbd0.00 B28-04-16|14:14
AND2X1.mod0.00 B28-04-16|14:14
AND2X2.mod0.00 B28-04-16|14:14
AOI21X1.mod0.00 B28-04-16|14:14
AOI22X1.mod0.00 B28-04-16|14:14
BUFX2.mod0.00 B28-04-16|14:14
BUFX4.mod0.00 B28-04-16|14:14
CLKBUF1.mod0.00 B28-04-16|14:14
CLKBUF2.mod0.00 B28-04-16|14:14
CLKBUF3.mod0.00 B28-04-16|14:14
DFFNEGX1.mod0.00 B28-04-16|14:14
DFFPOSX1.mod0.00 B28-04-16|14:14
DFFSR.mod0.00 B28-04-16|14:14
FAX1.mod0.00 B28-04-16|14:14
HAX1.mod0.00 B28-04-16|14:14
INVX1.mod0.00 B28-04-16|14:14
INVX2.mod0.00 B28-04-16|14:14
INVX4.mod0.00 B28-04-16|14:14
INVX8.mod0.00 B28-04-16|14:14
LATCH.mod0.00 B28-04-16|14:14
MUX2X1.mod0.00 B28-04-16|14:14
NAND2X1.mod0.00 B28-04-16|14:14
NAND3X1.mod0.00 B28-04-16|14:14
NOR2X1.mod0.00 B28-04-16|14:14
NOR3X1.mod0.00 B28-04-16|14:14
OAI21X1.mod0.00 B28-04-16|14:14
OAI22X1.mod0.00 B28-04-16|14:14
OR2X1.mod0.00 B28-04-16|14:14
OR2X2.mod0.00 B28-04-16|14:14
TBUFX1.mod0.00 B28-04-16|14:14
TBUFX2.mod0.00 B28-04-16|14:14
udp_dff.udp0.00 B28-04-16|14:14
udp_mux2.udp0.00 B28-04-16|14:14
udp_rslat.udp0.00 B28-04-16|14:14
udp_tlat.udp0.00 B28-04-16|14:14
XNOR2X1.mod0.00 B28-04-16|14:14
XOR2X1.mod0.00 B28-04-16|14:14
adder.mod0.00 B28-04-16|14:14
adder_32.mod0.00 B28-04-16|14:14
addsub_32.mod0.00 B28-04-16|14:14
alu_32.mod0.00 B28-04-16|14:14
and_32.mod0.00 B28-04-16|14:14
compare_32.mod0.00 B28-04-16|14:14
control.mod0.00 B28-04-16|14:14
cpu32.mod0.00 B28-04-16|14:14
decoder2to4.mod0.00 B28-04-16|14:14
decoder3to8.mod0.00 B28-04-16|14:14
decoder4to16.mod0.00 B28-04-16|14:14
dff.mod0.00 B28-04-16|14:14
dff_32.mod0.00 B28-04-16|14:14
dff_8.mod0.00 B28-04-16|14:14
inc_8.mod0.00 B28-04-16|14:14
memory16_32.mod0.00 B28-04-16|14:14
memory_32.mod0.00 B28-04-16|14:14
mux2to1.mod0.00 B28-04-16|14:14
mux2to1_32.mod0.00 B28-04-16|14:14
mux2to1_8.mod0.00 B28-04-16|14:14
PC.mod0.00 B28-04-16|14:14
shift_left_logic_32.mod0.00 B28-04-16|14:14
shift_right_logic_32.mod0.00 B28-04-16|14:14
tris.mod0.00 B28-04-16|14:14
tris_32.mod0.00 B28-04-16|14:14
xnor_32.mod0.00 B28-04-16|14:14
GTECH_COMPONENTS.pbd0.00 B28-04-16|14:14
AND2X1.mod0.00 B28-04-16|14:14
AND2X2.mod0.00 B28-04-16|14:14
AOI21X1.mod0.00 B28-04-16|14:14
AOI22X1.mod0.00 B28-04-16|14:14
BUFX2.mod0.00 B28-04-16|14:14
BUFX4.mod0.00 B28-04-16|14:14
CLKBUF1.mod0.00 B28-04-16|14:14
CLKBUF2.mod0.00 B28-04-16|14:14
CLKBUF3.mod0.00 B28-04-16|14:14
DFFNEGX1.mod0.00 B28-04-16|14:14
DFFPOSX1.mod0.00 B28-04-16|14:14
DFFSR.mod0.00 B28-04-16|14:14
FAX1.mod0.00 B28-04-16|14:14
HAX1.mod0.00 B28-04-16|14:14
INVX1.mod0.00 B28-04-16|14:14
INVX2.mod0.00 B28-04-16|14:14
INVX4.mod0.00 B28-04-16|14:14
INVX8.mod0.00 B28-04-16|14:14
LATCH.mod0.00 B28-04-16|14:14
MUX2X1.mod0.00 B28-04-16|14:14
NAND2X1.mod0.00 B28-04-16|14:14
NAND3X1.mod0.00 B28-04-16|14:14
NOR2X1.mod0.00 B28-04-16|14:14
NOR3X1.mod0.00 B28-04-16|14:14
OAI21X1.mod0.00 B28-04-16|14:14
OAI22X1.mod0.00 B28-04-16|14:14
OR2X1.mod0.00 B28-04-16|14:14
OR2X2.mod0.00 B28-04-16|14:14
TBUFX1.mod0.00 B28-04-16|14:14
TBUFX2.mod0.00 B28-04-16|14:14
udp_dff.udp0.00 B28-04-16|14:14
udp_mux2.udp0.00 B28-04-16|14:14
udp_rslat.udp0.00 B28-04-16|14:14
udp_tlat.udp0.00 B28-04-16|14:14
XNOR2X1.mod0.00 B28-04-16|14:14
XOR2X1.mod0.00 B28-04-16|14:14
adder.mod0.00 B28-04-16|14:14
adder_32.mod0.00 B28-04-16|14:14
addsub_32.mod0.00 B28-04-16|14:14
alu_32.mod0.00 B28-04-16|14:14
and_32.mod0.00 B28-04-16|14:14
compare_32.mod0.00 B28-04-16|14:14
control.mod0.00 B28-04-16|14:14
cpu32.mod0.00 B28-04-16|14:14
decoder2to4.mod0.00 B28-04-16|14:14
decoder3to8.mod0.00 B28-04-16|14:14
decoder4to16.mod0.00 B28-04-16|14:14
dff.mod0.00 B28-04-16|14:14
dff_32.mod0.00 B28-04-16|14:14
dff_8.mod0.00 B28-04-16|14:14
inc_8.mod0.00 B28-04-16|14:14
memory16_32.mod0.00 B28-04-16|14:14
memory_32.mod0.00 B28-04-16|14:14
mux2to1.mod0.00 B28-04-16|14:14
mux2to1_32.mod0.00 B28-04-16|14:14
mux2to1_8.mod0.00 B28-04-16|14:14
PC.mod0.00 B28-04-16|14:14
shift_left_logic_32.mod0.00 B28-04-16|14:14
shift_right_logic_32.mod0.00 B28-04-16|14:14
tris.mod0.00 B28-04-16|14:14
tris_32.mod0.00 B28-04-16|14:14
xnor_32.mod0.00 B28-04-16|14:14
GTECH_COMPONENTS.pbd0.00 B28-04-16|14:14
AND2X1.mod0.00 B28-04-16|14:14
AND2X2.mod0.00 B28-04-16|14:14
AOI21X1.mod0.00 B28-04-16|14:14
AOI22X1.mod0.00 B28-04-16|14:14
BUFX2.mod0.00 B28-04-16|14:14
BUFX4.mod0.00 B28-04-16|14:14
CLKBUF1.mod0.00 B28-04-16|14:14
CLKBUF2.mod0.00 B28-04-16|14:14
CLKBUF3.mod0.00 B28-04-16|14:14
DFFNEGX1.mod0.00 B28-04-16|14:14
DFFPOSX1.mod0.00 B28-04-16|14:14
DFFSR.mod0.00 B28-04-16|14:14
FAX1.mod0.00 B28-04-16|14:14
HAX1.mod0.00 B28-04-16|14:14
INVX1.mod0.00 B28-04-16|14:14
INVX2.mod0.00 B28-04-16|14:14
INVX4.mod0.00 B28-04-16|14:14
INVX8.mod0.00 B28-04-16|14:14
LATCH.mod0.00 B28-04-16|14:14
MUX2X1.mod0.00 B28-04-16|14:14
NAND2X1.mod0.00 B28-04-16|14:14
NAND3X1.mod0.00 B28-04-16|14:14
NOR2X1.mod0.00 B28-04-16|14:14
NOR3X1.mod0.00 B28-04-16|14:14
OAI21X1.mod0.00 B28-04-16|14:14
OAI22X1.mod0.00 B28-04-16|14:14
OR2X1.mod0.00 B28-04-16|14:14
OR2X2.mod0.00 B28-04-16|14:14
TBUFX1.mod0.00 B28-04-16|14:14
TBUFX2.mod0.00 B28-04-16|14:14
udp_dff.udp0.00 B28-04-16|14:14
udp_mux2.udp0.00 B28-04-16|14:14
udp_rslat.udp0.00 B28-04-16|14:14
udp_tlat.udp0.00 B28-04-16|14:14
XNOR2X1.mod0.00 B28-04-16|14:14
XOR2X1.mod0.00 B28-04-16|14:14
adder.mod0.00 B28-04-16|14:14
adder_32.mod0.00 B28-04-16|14:14
addsub_32.mod0.00 B28-04-16|14:14
alu_32.mod0.00 B28-04-16|14:14
and_32.mod0.00 B28-04-16|14:14
compare_32.mod0.00 B28-04-16|14:14
control.mod0.00 B28-04-16|14:14
cpu32.mod0.00 B28-04-16|14:14
decoder2to4.mod0.00 B28-04-16|14:14
decoder3to8.mod0.00 B28-04-16|14:14
decoder4to16.mod0.00 B28-04-16|14:14
dff.mod0.00 B28-04-16|14:14
dff_32.mod0.00 B28-04-16|14:14
dff_8.mod0.00 B28-04-16|14:14
inc_8.mod0.00 B28-04-16|14:14
memory16_32.mod0.00 B28-04-16|14:14
memory_32.mod0.00 B28-04-16|14:14
mux2to1.mod0.00 B28-04-16|14:14
mux2to1_32.mod0.00 B28-04-16|14:14
mux2to1_8.mod0.00 B28-04-16|14:14
PC.mod0.00 B28-04-16|14:14
shift_left_logic_32.mod0.00 B28-04-16|14:14
shift_right_logic_32.mod0.00 B28-04-16|14:14
tris.mod0.00 B28-04-16|14:14
tris_32.mod0.00 B28-04-16|14:14
xnor_32.mod0.00 B28-04-16|14:14
workspaces0.00 B28-04-16|14:14
GTECH_COMPONENTS.pkg0.00 B28-04-16|14:14
GTECH_COMPONENTS.pkg0.00 B28-04-16|14:14
TECH_WORK0.00 B28-04-16|14:14
WORK0.00 B28-04-16|14:14
WORK0.00 B28-04-16|14:14
GTECH_COMPONENTS.pkg0.00 B28-04-16|14:14
TECH_WORK0.00 B28-04-16|14:14
WORK0.00 B28-04-16|14:14
WORK0.00 B28-04-16|14:14
GTECH_COMPONENTS.pkg0.00 B28-04-16|14:14
TECH_WORK0.00 B28-04-16|14:14
WORK0.00 B28-04-16|14:14
WORK0.00 B28-04-16|14:14
viva0.00 B28-04-16|14:15
workspaces0.00 B28-04-16|14:15
edi0.00 B28-04-16|14:14
GTECH0.00 B28-04-16|14:14
i0.00 B28-04-16|14:14
r0.00 B28-04-16|14:14
server0.00 B28-04-16|14:14
GTECH0.00 B28-04-16|14:14
i0.00 B28-04-16|14:14
r0.00 B28-04-16|14:14
server0.00 B28-04-16|14:14
GTECH0.00 B28-04-16|14:14
i0.00 B28-04-16|14:14
r0.00 B28-04-16|14:14
server0.00 B28-04-16|14:14
GTECH0.00 B28-04-16|14:14
i0.00 B28-04-16|14:14
r0.00 B28-04-16|14:14
server0.00 B28-04-16|14:14
dfII0.00 B28-04-16|14:15
edi0.00 B28-04-16|14:15
.cadence0.00 B28-04-16|14:14
.simvision0.00 B28-04-16|14:14
FM_WORK0.00 B28-04-16|14:14
FM_WORK10.00 B28-04-16|14:14
FM_WORK20.00 B28-04-16|14:14
FM_WORK30.00 B28-04-16|14:14
shm.db0.00 B28-04-16|14:15
WORK0.00 B28-04-16|14:14
.cadence0.00 B28-04-16|14:15
shm.db0.00 B28-04-16|14:15
WORK0.00 B28-04-16|14:15
carry_ripple0.00 B28-04-16|14:15
carry_skip0.00 B28-04-16|14:15
code.hex67.00 B03-05-16|20:58
cpu32_cmp.v18.17 kB24-04-16|17:36
cpu32_test.v2.04 kB19-04-16|22:38
bonus0.00 B03-05-16|20:56
...
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gscl45nm.v (9.83 MB)

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