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			// Copyright (c) 2008-2014 Illinois Institute of Technology
//               All rights reserved.
// Author:       Jia Wang, jwang@ece.iit,edu

// Basic circuit elements

module decoder2to4(in, out, en);
   
   output [3:0] out;
   input [1:0] 	in;
   input 	en;
   
   wire [1:0] 	nn;
   
   not(nn[0], in[0]);
   not(nn[1], in[1]);
   
   and(out[0], nn[1], nn[0], en);
   and(out[1], nn[1], in[0], en);
   and(out[2], in[1], nn[0], en);
   and(out[3], in[1], in[0], en);

endmodule // decoder2to4


module decoder3to8(in, out, en);
   
   output [7:0] out;
   input [2:0] 	in;
   input 	en;
   
   wire 	nn2, en0, en1;
   
   not(nn2, in[2]);
   and(en0, nn2, en);
   and(en1, in[2], en);
   
   decoder2to4 d0(in[1:0], out[3:0], en0);
   decoder2to4 d1(in[1:0], out[7:4], en1);
   
endmodule // decoder3to8


module decoder4to16(in, out, en);

   output [15:0] out;
   input [3:0] 	 in;
   input 	 en;
   
   wire 	 nn3, en0, en1;
   
   not(nn3, in[3]);
   and(en0, nn3, en);
   and(en1, in[3], en);
   
   decoder3to8 d0(in[2:0], out[7:0], en0);
   decoder3to8 d1(in[2:0], out[15:8], en1);
   
endmodule // decoder4to16


module tris(in, sel, out);
   
   output out;
   input  in, sel;
   tri 	  out;
   
   bufif1 b1(out, in, sel);
   
endmodule // tris


module tris_32(in, sel, out);
   
   output [31:0] out;
   input [31:0] in;
   input 	sel;
   
   tris t0(in[0], sel, out[0]);
   tris t1(in[1], sel, out[1]);
   tris t2(in[2], sel, out[2]);
   tris t3(in[3], sel, out[3]);
   tris t4(in[4], sel, out[4]);
   tris t5(in[5], sel, out[5]);
   tris t6(in[6], sel, out[6]);
   tris t7(in[7], sel, out[7]);
   tris t8(in[8], sel, out[8]);
   tris t9(in[9], sel, out[9]);
   tris t10(in[10], sel, out[10]);
   tris t11(in[11], sel, out[11]);
   tris t12(in[12], sel, out[12]);
   tris t13(in[13], sel, out[13]);
   tris t14(in[14], sel, out[14]);
   tris t15(in[15], sel, out[15]);
   tris t16(in[16], sel, out[16]);
   tris t17(in[17], sel, out[17]);
   tris t18(in[18], sel, out[18]);
   tris t19(in[19], sel, out[19]);
   tris t20(in[20], sel, out[20]);
   tris t21(in[21], sel, out[21]);
   tris t22(in[22], sel, out[22]);
   tris t23(in[23], sel, out[23]);
   tris t24(in[24], sel, out[24]);
   tris t25(in[25], sel, out[25]);
   tris t26(in[26], sel, out[26]);
   tris t27(in[27], sel, out[27]);
   tris t28(in[28], sel, out[28]);
   tris t29(in[29], sel, out[29]);
   tris t30(in[30], sel, out[30]);
   tris t31(in[31], sel, out[31]);

endmodule // tris_32


module dff(d, clk, q);
   
   output q;
   input  d, clk;
   reg 	  q;
   
   always @(posedge clk)
     q <= d;
   
endmodule // dff


module dff_8(d, clk, q);
   
   output [7:0] q;
   input [7:0] 	d;
   input 	clk;	
   
   dff d0(d[0], clk, q[0]);
   dff d1(d[1], clk, q[1]);
   dff d2(d[2], clk, q[2]);
   dff d3(d[3], clk, q[3]);
   dff d4(d[4], clk, q[4]);
   dff d5(d[5], clk, q[5]);
   dff d6(d[6], clk, q[6]);
   dff d7(d[7], clk, q[7]);

endmodule // dff_8


module dff_32(d, clk, q);
   
   output [31:0] q;
   input [31:0] 	d;
   input 	clk;	
   
   dff d0(d[0], clk, q[0]);
   dff d1(d[1], clk, q[1]);
   dff d2(d[2], clk, q[2]);
   dff d3(d[3], clk, q[3]);
   dff d4(d[4], clk, q[4]);
   dff d5(d[5], clk, q[5]);
   dff d6(d[6], clk, q[6]);
   dff d7(d[7], clk, q[7]);
   dff d8(d[8], clk, q[8]);
   dff d9(d[9], clk, q[9]);
   dff d10(d[10], clk, q[10]);
   dff d11(d[11], clk, q[11]);
   dff d12(d[12], clk, q[12]);
   dff d13(d[13], clk, q[13]);
   dff d14(d[14], clk, q[14]);
   dff d15(d[15], clk, q[15]);
   dff d16(d[16], clk, q[16]);
   dff d17(d[17], clk, q[17]);
   dff d18(d[18], clk, q[18]);
   dff d19(d[19], clk, q[19]);
   dff d20(d[20], clk, q[20]);
   dff d21(d[21], clk, q[21]);
   dff d22(d[22], clk, q[22]);
   dff d23(d[23], clk, q[23]);
   dff d24(d[24], clk, q[24]);
   dff d25(d[25], clk, q[25]);
   dff d26(d[26], clk, q[26]);
   dff d27(d[27], clk, q[27]);
   dff d28(d[28], clk, q[28]);
   dff d29(d[29], clk, q[29]);
   dff d30(d[30], clk, q[30]);
   dff d31(d[31], clk, q[31]);

endmodule // dff_32


module mux2to1(in0, in1, sel, out);
   
   output out;
   input  in0, in1, sel;
   
   wire   nsel, n0, n1;
   
   not(nsel, sel);
   
   and(n0, nsel, in0);
   and(n1, sel, in1);
   
   or(out, n0, n1);
   
endmodule // mux2to1


module mux2to1_8(in0, in1, sel, out);

   output [7:0] out;
   input [7:0] 	in0, in1;
   input 	sel;

   mux2to1 m0(in0[0], in1[0], sel, out[0]);
   mux2to1 m1(in0[1], in1[1], sel, out[1]);
   mux2to1 m2(in0[2], in1[2], sel, out[2]);
   mux2to1 m3(in0[3], in1[3], sel, out[3]);
   mux2to1 m4(in0[4], in1[4], sel, out[4]);
   mux2to1 m5(in0[5], in1[5], sel, out[5]);
   mux2to1 m6(in0[6], in1[6], sel, out[6]);
   mux2to1 m7(in0[7], in1[7], sel, out[7]);

endmodule // mux2to1_8


module mux2to1_32(in0, in1, sel, out);

   output [31:0] out;
   input [31:0] in0, in1;
   input 	sel;

   mux2to1 m0(in0[0], in1[0], sel, out[0]);
   mux2to1 m1(in0[1], in1[1], sel, out[1]);
   mux2to1 m2(in0[2], in1[2], sel, out[2]);
   mux2to1 m3(in0[3], in1[3], sel, out[3]);
   mux2to1 m4(in0[4], in1[4], sel, out[4]);
   mux2to1 m5(in0[5], in1[5], sel, out[5]);
   mux2to1 m6(in0[6], in1[6], sel, out[6]);
   mux2to1 m7(in0[7], in1[7], sel, out[7]);
   mux2to1 m8(in0[8], in1[8], sel, out[8]);
   mux2to1 m9(in0[9], in1[9], sel, out[9]);
   mux2to1 m10(in0[10], in1[10], sel, out[10]);
   mux2to1 m11(in0[11], in1[11], sel, out[11]);
   mux2to1 m12(in0[12], in1[12], sel, out[12]);
   mux2to1 m13(in0[13], in1[13], sel, out[13]);
   mux2to1 m14(in0[14], in1[14], sel, out[14]);
   mux2to1 m15(in0[15], in1[15], sel, out[15]);
   mux2to1 m16(in0[16], in1[16], sel, out[16]);
   mux2to1 m17(in0[17], in1[17], sel, out[17]);
   mux2to1 m18(in0[18], in1[18], sel, out[18]);
   mux2to1 m19(in0[19], in1[19], sel, out[19]);
   mux2to1 m20(in0[20], in1[20], sel, out[20]);
   mux2to1 m21(in0[21], in1[21], sel, out[21]);
   mux2to1 m22(in0[22], in1[22], sel, out[22]);
   mux2to1 m23(in0[23], in1[23], sel, out[23]);
   mux2to1 m24(in0[24], in1[24], sel, out[24]);
   mux2to1 m25(in0[25], in1[25], sel, out[25]);
   mux2to1 m26(in0[26], in1[26], sel, out[26]);
   mux2to1 m27(in0[27], in1[27], sel, out[27]);
   mux2to1 m28(in0[28], in1[28], sel, out[28]);
   mux2to1 m29(in0[29], in1[29], sel, out[29]);
   mux2to1 m30(in0[30], in1[30], sel, out[30]);
   mux2to1 m31(in0[31], in1[31], sel, out[31]);

   
endmodule // mux2to1_32


module memory_32(port_a, sel_a, port_b, sel_b, port_s, write_en, clk);
   
   output [31:0] port_a, port_b;
   input 	sel_a, sel_b, write_en, clk;
   input [31:0] 	port_s;
   
   wire [31:0] 	dout, mux_out;
   
   mux2to1_32 m0(dout, port_s, write_en, mux_out);
   
   dff_32 d(mux_out, clk, dout);
   
   tris_32 ta(dout, sel_a, port_a);
   tris_32 tb(dout, sel_b, port_b);
   
endmodule // memory_32


module memory16_32(port_a, addr_a, port_b, addr_b, port_s, addr_s, write_en, clk);
   
   output [31:0] port_a, port_b;
   input [3:0] 	addr_a, addr_b, addr_s;
   input 	write_en, clk;
   input [31:0] 	port_s;
   
   wire [15:0] 	sel_a, sel_b, sel_s;
   
   //Decoding address line
   decoder4to16 da(addr_a, sel_a, 1'b1);
   decoder4to16 db(addr_b, sel_b, 1'b1);
   decoder4to16 ds(addr_s, sel_s, write_en);

   memory_32 m0(port_a, sel_a[0], port_b, sel_b[0], port_s, sel_s[0], clk);
   memory_32 m1(port_a, sel_a[1], port_b, sel_b[1], port_s, sel_s[1], clk);
   memory_32 m2(port_a, sel_a[2], port_b, sel_b[2], port_s, sel_s[2], clk);
   memory_32 m3(port_a, sel_a[3], port_b, sel_b[3], port_s, sel_s[3], clk);
   memory_32 m4(port_a, sel_a[4], port_b, sel_b[4], port_s, sel_s[4], clk);
   memory_32 m5(port_a, sel_a[5], port_b, sel_b[5], port_s, sel_s[5], clk);
   memory_32 m6(port_a, sel_a[6], port_b, sel_b[6], port_s, sel_s[6], clk);
   memory_32 m7(port_a, sel_a[7], port_b, sel_b[7], port_s, sel_s[7], clk);
   memory_32 m8(port_a, sel_a[8], port_b, sel_b[8], port_s, sel_s[8], clk);
   memory_32 m9(port_a, sel_a[9], port_b, sel_b[9], port_s, sel_s[9], clk);
   memory_32 m10(port_a, sel_a[10], port_b, sel_b[10], port_s, sel_s[10], clk);
   memory_32 m11(port_a, sel_a[11], port_b, sel_b[11], port_s, sel_s[11], clk);
   memory_32 m12(port_a, sel_a[12], port_b, sel_b[12], port_s, sel_s[12], clk);
   memory_32 m13(port_a, sel_a[13], port_b, sel_b[13], port_s, sel_s[13], clk);
   memory_32 m14(port_a, sel_a[14], port_b, sel_b[14], port_s, sel_s[14], clk);
   memory_32 m15(port_a, sel_a[15], port_b, sel_b[15], port_s, sel_s[15], clk);
   
endmodule // memory16_32


// Logic module in ALU

module and_32(s, a, b);
   
   output [31:0] s;
   input [31:0] a,b;
   
   and myand[31:0](s, a, b);
   
endmodule // and_32

//comparator

module compare_32(cmp,a,b);

   input [31:0] a,b;
   //input [31:0] b;
   output  cmp;
   assign cmp=a>=b?1'b1:1'b0;

endmodule


module xnor_32(s, a, b);
   
   output [31:0] s;
   input [31:0] a,b;
   
   xnor myxnor[31:0](s, a, b);
   
endmodule // xnor_32


// Adder in ALU

module adder(s, co, a, b, ci);

   output s, co;
   input  a, b, ci;
   
   wire   o0, o1, o2;
   
   xor(s, a, b, ci);
   
   or(o0, a, b);
   or(o1, b, ci);
   or(o2, ci, a);
   and(co, o0, o1, o2);
   
endmodule // adder


module adder_32(s, co, of, a, b, ci);
   
   output [31:0] s;
   output 	co, of;
   input [31:0] a, b;
   input 	ci;
   
   wire 	c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13, c14, c15, c16, c17, c18, c19, c20, c21, c22, c23, c24, c25, c26, c27, c28, c29, c30, c31;
   
   adder a0(s[0], c1, a[0], b[0], ci);
   adder a1(s[1], c2, a[1], b[1], c1);
   adder a2(s[2], c3, a[2], b[2], c2);
   adder a3(s[3], c4, a[3], b[3], c3);
   adder a4(s[4], c5, a[4], b[4], c4);
   adder a5(s[5], c6, a[5], b[5], c5);
   adder a6(s[6], c7, a[6], b[6], c6);
   adder a7(s[7], c8, a[7], b[7], c7);
   adder a8(s[8], c9, a[8], b[8], c8);
   adder a9(s[9], c10, a[9], b[9], c9);
   adder a10(s[10], c11, a[10], b[10], c10);
   adder a11(s[11], c12, a[11], b[1
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AND2X1.dmp1.49 kB25-04-16|01:43
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AND2X2.dmp1.52 kB25-04-16|01:43
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AOI22X1.dmp3.12 kB25-04-16|01:43
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BUFX2.dmp1.10 kB25-04-16|01:43
BUFX2.recent2.00 B25-04-16|01:43
BUFX4.dmp1.14 kB25-04-16|01:43
BUFX4.recent2.00 B25-04-16|01:43
CLKBUF1.dmp1.15 kB25-04-16|01:43
CLKBUF1.recent2.00 B25-04-16|01:43
CLKBUF2.dmp1.17 kB25-04-16|01:43
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CLKBUF3.dmp1.18 kB25-04-16|01:43
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DFFNEGX1.dmp4.21 kB25-04-16|01:43
DFFNEGX1.recent2.00 B25-04-16|01:43
DFFPOSX1.dmp3.99 kB25-04-16|01:43
DFFPOSX1.recent2.00 B25-04-16|01:43
DFFSR.dmp9.35 kB25-04-16|01:43
DFFSR.recent2.00 B25-04-16|01:43
FAX1.dmp4.82 kB25-04-16|01:43
FAX1.recent2.00 B25-04-16|01:43
HAX1.dmp2.94 kB25-04-16|01:43
HAX1.recent2.00 B25-04-16|01:43
INVX1.dmp1.27 kB25-04-16|01:43
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INVX2.dmp1.30 kB25-04-16|01:43
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INVX4.dmp1.31 kB25-04-16|01:43
INVX4.recent2.00 B25-04-16|01:43
INVX8.dmp1.33 kB25-04-16|01:43
INVX8.recent2.00 B25-04-16|01:43
LATCH.dmp4.26 kB25-04-16|01:43
LATCH.recent2.00 B25-04-16|01:43
MUX2X1.dmp2.71 kB25-04-16|01:43
MUX2X1.recent2.00 B25-04-16|01:43
NAND2X1.dmp2.13 kB25-04-16|01:43
NAND2X1.recent2.00 B25-04-16|01:43
NAND3X1.dmp2.74 kB25-04-16|01:43
NAND3X1.recent2.00 B25-04-16|01:43
NOR2X1.dmp2.18 kB25-04-16|01:43
NOR2X1.recent2.00 B25-04-16|01:43
NOR3X1.dmp2.78 kB25-04-16|01:43
NOR3X1.recent2.00 B25-04-16|01:43
OAI21X1.dmp2.97 kB25-04-16|01:43
OAI21X1.recent2.00 B25-04-16|01:43
OAI22X1.dmp3.76 kB25-04-16|01:43
OAI22X1.recent2.00 B25-04-16|01:43
OR2X1.dmp2.06 kB25-04-16|01:43
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OR2X2.dmp2.09 kB25-04-16|01:43
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TBUFX1.dmp2.64 kB25-04-16|01:43
TBUFX1.recent2.00 B25-04-16|01:43
TBUFX2.dmp2.67 kB25-04-16|01:43
TBUFX2.recent2.00 B25-04-16|01:43
udp_dff.dmp3.42 kB25-04-16|01:43
udp_mux2.dmp1.79 kB25-04-16|01:43
udp_rslat.dmp1.87 kB25-04-16|01:43
udp_tlat.dmp3.30 kB25-04-16|01:43
XNOR2X1.dmp2.31 kB25-04-16|01:43
XNOR2X1.recent2.00 B25-04-16|01:43
XOR2X1.dmp2.15 kB25-04-16|01:43
XOR2X1.recent2.00 B25-04-16|01:43
adder.dmp2.29 kB25-04-16|01:44
adder.recent2.00 B25-04-16|01:44
adder_32.dmp15.57 kB25-04-16|01:44
adder_32.recent2.00 B25-04-16|01:44
addsub_32.dmp9.90 kB25-04-16|01:44
addsub_32.recent2.00 B25-04-16|01:44
alu_32.dmp5.42 kB25-04-16|01:44
alu_32.recent2.00 B25-04-16|01:44
and_32.dmp1.29 kB25-04-16|01:44
and_32.recent2.00 B25-04-16|01:44
compare_32.dmp1.24 kB25-04-16|01:44
compare_32.recent2.00 B25-04-16|01:44
control.dmp7.91 kB25-04-16|01:44
control.recent2.00 B25-04-16|01:44
cpu32.dmp8.55 kB25-04-16|01:44
cpu32.recent2.00 B25-04-16|01:44
decoder2to4.dmp2.25 kB25-04-16|01:44
decoder2to4.recent2.00 B25-04-16|01:44
decoder3to8.dmp1.85 kB25-04-16|01:44
decoder3to8.recent2.00 B25-04-16|01:44
decoder4to16.dmp1.88 kB25-04-16|01:44
decoder4to16.recent2.00 B25-04-16|01:44
dff.dmp987.00 B25-04-16|01:44
dff.recent2.00 B25-04-16|01:44
dff_32.dmp8.89 kB25-04-16|01:44
dff_32.recent2.00 B25-04-16|01:44
dff_8.dmp2.85 kB25-04-16|01:44
dff_8.recent2.00 B25-04-16|01:44
inc_8.dmp4.13 kB25-04-16|01:44
inc_8.recent2.00 B25-04-16|01:44
memory16_32.dmp10.36 kB25-04-16|01:44
memory16_32.recent2.00 B25-04-16|01:44
memory_32.dmp2.69 kB25-04-16|01:44
memory_32.recent2.00 B25-04-16|01:44
mux2to1.dmp1.73 kB25-04-16|01:44
mux2to1.recent2.00 B25-04-16|01:44
mux2to1_32.dmp11.82 kB25-04-16|01:44
mux2to1_32.recent2.00 B25-04-16|01:44
mux2to1_8.dmp3.82 kB25-04-16|01:44
mux2to1_8.recent2.00 B25-04-16|01:44
PC.dmp3.50 kB25-04-16|01:44
PC.recent2.00 B25-04-16|01:44
shift_left_logic_32.dmp4.57 kB25-04-16|01:44
shift_left_logic_32.recent2.00 B25-04-16|01:44
shift_right_logic_32.dmp4.61 kB25-04-16|01:44
shift_right_logic_32.recent2.00 B25-04-16|01:44
tris.dmp927.00 B25-04-16|01:44
tris.recent2.00 B25-04-16|01:44
tris_32.dmp8.15 kB25-04-16|01:44
tris_32.recent2.00 B25-04-16|01:44
xnor_32.dmp1.33 kB25-04-16|01:44
xnor_32.recent2.00 B25-04-16|01:44
_license_string23.00 B24-04-16|20:36
GTECH_COMPONENTS.dep347.00 B25-04-16|02:05
GTECH_COMPONENTS.dmp21.61 kB25-04-16|02:05
GTECH_COMPONENTS.dep117.00 B25-04-16|02:05
GTECH_COMPONENTS.dmp1.68 kB25-04-16|02:05
AND2X1.dmp1.49 kB25-04-16|02:10
AND2X1.recent2.00 B25-04-16|02:10
AND2X2.dmp1.52 kB25-04-16|02:10
AND2X2.recent2.00 B25-04-16|02:10
AOI21X1.dmp2.40 kB25-04-16|02:10
AOI21X1.recent2.00 B25-04-16|02:10
AOI22X1.dmp3.12 kB25-04-16|02:10
AOI22X1.recent2.00 B25-04-16|02:10
BUFX2.dmp1.10 kB25-04-16|02:10
BUFX2.recent2.00 B25-04-16|02:10
BUFX4.dmp1.14 kB25-04-16|02:10
BUFX4.recent2.00 B25-04-16|02:10
CLKBUF1.dmp1.15 kB25-04-16|02:10
CLKBUF1.recent2.00 B25-04-16|02:10
CLKBUF2.dmp1.17 kB25-04-16|02:10
CLKBUF2.recent2.00 B25-04-16|02:10
CLKBUF3.dmp1.18 kB25-04-16|02:10
CLKBUF3.recent2.00 B25-04-16|02:10
DFFNEGX1.dmp4.21 kB25-04-16|02:10
DFFNEGX1.recent2.00 B25-04-16|02:10
DFFPOSX1.dmp3.99 kB25-04-16|02:10
DFFPOSX1.recent2.00 B25-04-16|02:10
DFFSR.dmp9.35 kB25-04-16|02:10
DFFSR.recent2.00 B25-04-16|02:10
FAX1.dmp4.82 kB25-04-16|02:10
FAX1.recent2.00 B25-04-16|02:10
HAX1.dmp2.94 kB25-04-16|02:10
HAX1.recent2.00 B25-04-16|02:10
INVX1.dmp1.27 kB25-04-16|02:10
INVX1.recent2.00 B25-04-16|02:10
INVX2.dmp1.30 kB25-04-16|02:10
INVX2.recent2.00 B25-04-16|02:10
INVX4.dmp1.31 kB25-04-16|02:10
INVX4.recent2.00 B25-04-16|02:10
INVX8.dmp1.33 kB25-04-16|02:10
INVX8.recent2.00 B25-04-16|02:10
LATCH.dmp4.26 kB25-04-16|02:10
LATCH.recent2.00 B25-04-16|02:10
MUX2X1.dmp2.71 kB25-04-16|02:10
MUX2X1.recent2.00 B25-04-16|02:10
NAND2X1.dmp2.13 kB25-04-16|02:10
NAND2X1.recent2.00 B25-04-16|02:10
NAND3X1.dmp2.74 kB25-04-16|02:10
NAND3X1.recent2.00 B25-04-16|02:10
NOR2X1.dmp2.18 kB25-04-16|02:10
NOR2X1.recent2.00 B25-04-16|02:10
NOR3X1.dmp2.78 kB25-04-16|02:10
NOR3X1.recent2.00 B25-04-16|02:10
OAI21X1.dmp2.97 kB25-04-16|02:10
OAI21X1.recent2.00 B25-04-16|02:10
OAI22X1.dmp3.76 kB25-04-16|02:10
OAI22X1.recent2.00 B25-04-16|02:10
OR2X1.dmp2.06 kB25-04-16|02:10
OR2X1.recent2.00 B25-04-16|02:10
OR2X2.dmp2.09 kB25-04-16|02:10
OR2X2.recent2.00 B25-04-16|02:10
TBUFX1.dmp2.64 kB25-04-16|02:10
TBUFX1.recent2.00 B25-04-16|02:10
TBUFX2.dmp2.67 kB25-04-16|02:10
TBUFX2.recent2.00 B25-04-16|02:10
udp_dff.dmp3.42 kB25-04-16|02:10
udp_mux2.dmp1.79 kB25-04-16|02:10
udp_rslat.dmp1.87 kB25-04-16|02:10
udp_tlat.dmp3.30 kB25-04-16|02:10
XNOR2X1.dmp2.31 kB25-04-16|02:10
XNOR2X1.recent2.00 B25-04-16|02:10
XOR2X1.dmp2.15 kB25-04-16|02:10
XOR2X1.recent2.00 B25-04-16|02:10
adder.dmp2.29 kB25-04-16|02:06
adder.recent2.00 B25-04-16|02:06
adder_32.dmp15.57 kB25-04-16|02:06
adder_32.recent2.00 B25-04-16|02:06
addsub_32.dmp9.90 kB25-04-16|02:06
addsub_32.recent2.00 B25-04-16|02:06
alu_32.dmp5.42 kB25-04-16|02:06
alu_32.recent2.00 B25-04-16|02:06
and_32.dmp1.29 kB25-04-16|02:06
and_32.recent2.00 B25-04-16|02:06
compare_32.dmp1.24 kB25-04-16|02:06
compare_32.recent2.00 B25-04-16|02:06
control.dmp7.91 kB25-04-16|02:06
control.recent2.00 B25-04-16|02:06
cpu32.dmp8.55 kB25-04-16|02:06
cpu32.recent2.00 B25-04-16|02:06
decoder2to4.dmp2.25 kB25-04-16|02:06
decoder2to4.recent2.00 B25-04-16|02:06
decoder3to8.dmp1.85 kB25-04-16|02:06
decoder3to8.recent2.00 B25-04-16|02:06
decoder4to16.dmp1.88 kB25-04-16|02:06
decoder4to16.recent2.00 B25-04-16|02:06
dff.dmp987.00 B25-04-16|02:06
dff.recent2.00 B25-04-16|02:06
dff_32.dmp8.89 kB25-04-16|02:06
dff_32.recent2.00 B25-04-16|02:06
dff_8.dmp2.85 kB25-04-16|02:06
dff_8.recent2.00 B25-04-16|02:06
inc_8.dmp4.13 kB25-04-16|02:06
inc_8.recent2.00 B25-04-16|02:06
memory16_32.dmp10.36 kB25-04-16|02:06
memory16_32.recent2.00 B25-04-16|02:06
memory_32.dmp2.69 kB25-04-16|02:06
memory_32.recent2.00 B25-04-16|02:06
mux2to1.dmp1.73 kB25-04-16|02:06
mux2to1.recent2.00 B25-04-16|02:06
mux2to1_32.dmp11.82 kB25-04-16|02:06
mux2to1_32.recent2.00 B25-04-16|02:06
mux2to1_8.dmp3.82 kB25-04-16|02:06
mux2to1_8.recent2.00 B25-04-16|02:06
PC.dmp3.50 kB25-04-16|02:06
PC.recent2.00 B25-04-16|02:06
shift_left_logic_32.dmp4.57 kB25-04-16|02:06
shift_left_logic_32.recent2.00 B25-04-16|02:06
shift_right_logic_32.dmp4.61 kB25-04-16|02:06
shift_right_logic_32.recent2.00 B25-04-16|02:06
tris.dmp927.00 B25-04-16|02:06
tris.recent2.00 B25-04-16|02:06
tris_32.dmp8.15 kB25-04-16|02:06
tris_32.recent2.00 B25-04-16|02:06
xnor_32.dmp1.33 kB25-04-16|02:06
xnor_32.recent2.00 B25-04-16|02:06
_license_string23.00 B25-04-16|02:05
GTECH_COMPONENTS.dep347.00 B25-04-16|05:37
GTECH_COMPONENTS.dmp21.61 kB25-04-16|05:37
GTECH_COMPONENTS.dep117.00 B25-04-16|05:37
GTECH_COMPONENTS.dmp1.68 kB25-04-16|05:37
AND2X1.dmp1.49 kB25-04-16|05:38
AND2X1.recent2.00 B25-04-16|05:38
AND2X2.dmp1.52 kB25-04-16|05:38
AND2X2.recent2.00 B25-04-16|05:38
AOI21X1.dmp2.40 kB25-04-16|05:38
AOI21X1.recent2.00 B25-04-16|05:38
AOI22X1.dmp3.12 kB25-04-16|05:38
AOI22X1.recent2.00 B25-04-16|05:38
BUFX2.dmp1.10 kB25-04-16|05:38
BUFX2.recent2.00 B25-04-16|05:38
BUFX4.dmp1.14 kB25-04-16|05:38
BUFX4.recent2.00 B25-04-16|05:38
CLKBUF1.dmp1.15 kB25-04-16|05:38
CLKBUF1.recent2.00 B25-04-16|05:38
CLKBUF2.dmp1.17 kB25-04-16|05:38
CLKBUF2.recent2.00 B25-04-16|05:38
CLKBUF3.dmp1.18 kB25-04-16|05:38
CLKBUF3.recent2.00 B25-04-16|05:38
DFFNEGX1.dmp4.21 kB25-04-16|05:38
DFFNEGX1.recent2.00 B25-04-16|05:38
DFFPOSX1.dmp3.99 kB25-04-16|05:38
DFFPOSX1.recent2.00 B25-04-16|05:38
DFFSR.dmp9.35 kB25-04-16|05:38
DFFSR.recent2.00 B25-04-16|05:38
FAX1.dmp4.82 kB25-04-16|05:38
FAX1.recent2.00 B25-04-16|05:38
HAX1.dmp2.94 kB25-04-16|05:38
HAX1.recent2.00 B25-04-16|05:38
INVX1.dmp1.27 kB25-04-16|05:38
INVX1.recent2.00 B25-04-16|05:38
INVX2.dmp1.30 kB25-04-16|05:38
INVX2.recent2.00 B25-04-16|05:38
INVX4.dmp1.31 kB25-04-16|05:38
INVX4.recent2.00 B25-04-16|05:38
INVX8.dmp1.33 kB25-04-16|05:38
INVX8.recent2.00 B25-04-16|05:38
LATCH.dmp4.26 kB25-04-16|05:38
LATCH.recent2.00 B25-04-16|05:38
MUX2X1.dmp2.71 kB25-04-16|05:38
MUX2X1.recent2.00 B25-04-16|05:38
NAND2X1.dmp2.13 kB25-04-16|05:38
NAND2X1.recent2.00 B25-04-16|05:38
NAND3X1.dmp2.74 kB25-04-16|05:38
NAND3X1.recent2.00 B25-04-16|05:38
NOR2X1.dmp2.18 kB25-04-16|05:38
NOR2X1.recent2.00 B25-04-16|05:38
NOR3X1.dmp2.78 kB25-04-16|05:38
NOR3X1.recent2.00 B25-04-16|05:38
OAI21X1.dmp2.97 kB25-04-16|05:38
OAI21X1.recent2.00 B25-04-16|05:38
OAI22X1.dmp3.76 kB25-04-16|05:38
OAI22X1.recent2.00 B25-04-16|05:38
OR2X1.dmp2.06 kB25-04-16|05:38
OR2X1.recent2.00 B25-04-16|05:38
OR2X2.dmp2.09 kB25-04-16|05:38
OR2X2.recent2.00 B25-04-16|05:38
TBUFX1.dmp2.64 kB25-04-16|05:38
TBUFX1.recent2.00 B25-04-16|05:38
TBUFX2.dmp2.67 kB25-04-16|05:38
TBUFX2.recent2.00 B25-04-16|05:38
udp_dff.dmp3.42 kB25-04-16|05:38
udp_mux2.dmp1.79 kB25-04-16|05:38
udp_rslat.dmp1.87 kB25-04-16|05:38
udp_tlat.dmp3.30 kB25-04-16|05:38
XNOR2X1.dmp2.31 kB25-04-16|05:38
XNOR2X1.recent2.00 B25-04-16|05:38
XOR2X1.dmp2.15 kB25-04-16|05:38
XOR2X1.recent2.00 B25-04-16|05:38
adder.dmp2.29 kB25-04-16|05:37
adder.recent2.00 B25-04-16|05:37
adder_32.dmp15.57 kB25-04-16|05:37
adder_32.recent2.00 B25-04-16|05:37
addsub_32.dmp9.90 kB25-04-16|05:37
addsub_32.recent2.00 B25-04-16|05:37
alu_32.dmp5.42 kB25-04-16|05:37
alu_32.recent2.00 B25-04-16|05:37
and_32.dmp1.29 kB25-04-16|05:37
and_32.recent2.00 B25-04-16|05:37
compare_32.dmp1.24 kB25-04-16|05:37
compare_32.recent2.00 B25-04-16|05:37
control.dmp7.91 kB25-04-16|05:37
control.recent2.00 B25-04-16|05:37
cpu32.dmp8.55 kB25-04-16|05:37
cpu32.recent2.00 B25-04-16|05:37
decoder2to4.dmp2.25 kB25-04-16|05:37
decoder2to4.recent2.00 B25-04-16|05:37
decoder3to8.dmp1.85 kB25-04-16|05:37
decoder3to8.recent2.00 B25-04-16|05:37
decoder4to16.dmp1.88 kB25-04-16|05:37
decoder4to16.recent2.00 B25-04-16|05:37
dff.dmp987.00 B25-04-16|05:37
dff.recent2.00 B25-04-16|05:37
dff_32.dmp8.89 kB25-04-16|05:37
dff_32.recent2.00 B25-04-16|05:37
dff_8.dmp2.85 kB25-04-16|05:37
dff_8.recent2.00 B25-04-16|05:37
inc_8.dmp4.13 kB25-04-16|05:37
inc_8.recent2.00 B25-04-16|05:37
memory16_32.dmp10.36 kB25-04-16|05:37
memory16_32.recent2.00 B25-04-16|05:37
memory_32.dmp2.69 kB25-04-16|05:37
memory_32.recent2.00 B25-04-16|05:37
mux2to1.dmp1.73 kB25-04-16|05:37
mux2to1.recent2.00 B25-04-16|05:37
mux2to1_32.dmp11.82 kB25-04-16|05:37
mux2to1_32.recent2.00 B25-04-16|05:37
mux2to1_8.dmp3.82 kB25-04-16|05:37
mux2to1_8.recent2.00 B25-04-16|05:37
PC.dmp3.50 kB25-04-16|05:37
PC.recent2.00 B25-04-16|05:37
shift_left_logic_32.dmp4.57 kB25-04-16|05:37
shift_left_logic_32.recent2.00 B25-04-16|05:37
shift_right_logic_32.dmp4.61 kB25-04-16|05:37
shift_right_logic_32.recent2.00 B25-04-16|05:37
tris.dmp927.00 B25-04-16|05:37
tris.recent2.00 B25-04-16|05:37
tris_32.dmp8.15 kB25-04-16|05:37
tris_32.recent2.00 B25-04-16|05:37
xnor_32.dmp1.33 kB25-04-16|05:37
xnor_32.recent2.00 B25-04-16|05:37
_license_string24.00 B25-04-16|05:37
formality.lck0.00 B24-04-16|19:04
formality.log0.00 B24-04-16|19:04
formality1.lck0.00 B24-04-16|20:36
formality1.log49.08 kB25-04-16|01:46
formality2.lck0.00 B25-04-16|02:05
formality2.log16.67 kB25-04-16|02:11
formality3.lck0.00 B25-04-16|05:37
formality3.log16.67 kB25-04-16|05:38
formality4.log13.72 kB25-04-16|06:09
gds2_encounter.map2.08 kB07-04-16|14:58
gds2_virtuoso.map1.20 kB07-04-16|14:58
gscl45nm.v21.99 kB07-04-16|14:58
ipo1.txt356.00 B25-04-16|06:06
ipo2.txt356.00 B25-04-16|06:07
power.final3.92 kB25-04-16|06:08
power.rep2.14 kB27-04-16|12:45
report.ctsmdl101.00 B25-04-16|06:07
report.ctsrpt44.20 kB25-04-16|06:07
report.post_troute.ctsrpt44.21 kB25-04-16|06:07
shm.dsn516.55 kB27-04-16|12:43
shm.trn1.79 MB27-04-16|12:43
skew.post_troute_local.ctsrpt44.39 kB25-04-16|06:07
timing.rep7.00 kB27-04-16|12:45
timing.rep.1.placed184.59 kB25-04-16|06:06
timing.rep.2.ipo1184.59 kB25-04-16|06:06
timing.rep.3.cts184.61 kB25-04-16|06:07
timing.rep.4.ipo2172.02 kB25-04-16|06:07
timing.rep.5.final172.02 kB25-04-16|06:08
verilog.log14.66 kB27-04-16|12:43
adder-verilog.pvl2.62 kB27-04-16|12:44
adder-verilog.syn280.00 B27-04-16|12:44
ADDER.mr23.00 B27-04-16|12:44
adder_32-verilog.pvl12.80 kB27-04-16|12:44
adder_32-verilog.syn285.00 B27-04-16|12:44
ADDER_32.mr23.00 B27-04-16|12:44
addsub_32-verilog.pvl7.85 kB27-04-16|12:44
addsub_32-verilog.syn284.00 B27-04-16|12:44
ADDSUB_32.mr23.00 B27-04-16|12:44
alu_32-verilog.pvl4.99 kB27-04-16|12:44
alu_32-verilog.syn283.00 B27-04-16|12:44
ALU_32.mr23.00 B27-04-16|12:44
and_32-verilog.pvl1.72 kB27-04-16|12:44
and_32-verilog.syn281.00 B27-04-16|12:44
AND_32.mr23.00 B27-04-16|12:44
compare_32-verilog.pvl1.59 kB25-04-16|02:17
compare_32-verilog.syn287.00 B25-04-16|02:17
COMPARE_32.mr23.00 B25-04-16|02:17
control-verilog.pvl5.92 kB27-04-16|12:44
control-verilog.syn284.00 B27-04-16|12:44
CONTROL.mr23.00 B27-04-16|12:44
cpu32-verilog.pvl6.95 kB27-04-16|12:44
cpu32-verilog.syn280.00 B27-04-16|12:44
CPU32.mr23.00 B27-04-16|12:44
decoder2to4-verilog.pvl2.71 kB27-04-16|12:44
decoder2to4-verilog.syn288.00 B27-04-16|12:44
DECODER2TO4.mr23.00 B27-04-16|12:44
decoder3to8-verilog.pvl2.61 kB27-04-16|12:44
decoder3to8-verilog.syn288.00 B27-04-16|12:44
DECODER3TO8.mr23.00 B27-04-16|12:44
decoder4to16-verilog.pvl2.61 kB27-04-16|12:44
decoder4to16-verilog.syn289.00 B27-04-16|12:44
DECODER4TO16.mr23.00 B27-04-16|12:44
dff-verilog.pvl1.54 kB27-04-16|12:44
dff-verilog.syn280.00 B27-04-16|12:44
DFF.mr23.00 B27-04-16|12:44
dff_32-verilog.pvl7.40 kB27-04-16|12:44
dff_32-verilog.syn283.00 B27-04-16|12:44
DFF_32.mr23.00 B27-04-16|12:44
dff_8-verilog.pvl2.94 kB27-04-16|12:44
dff_8-verilog.syn280.00 B27-04-16|12:44
DFF_8.mr23.00 B27-04-16|12:44
inc_8-verilog.pvl4.02 kB27-04-16|12:44
inc_8-verilog.syn282.00 B27-04-16|12:44
INC_8.mr23.00 B27-04-16|12:44
memory16_32-verilog.pvl7.35 kB27-04-16|12:44
memory16_32-verilog.syn288.00 B27-04-16|12:44
MEMORY16_32.mr23.00 B27-04-16|12:44
memory_32-verilog.pvl2.88 kB27-04-16|12:44
memory_32-verilog.syn286.00 B27-04-16|12:44
MEMORY_32.mr23.00 B27-04-16|12:44
mux2to1-verilog.pvl2.33 kB27-04-16|12:44
mux2to1-verilog.syn282.00 B27-04-16|12:44
MUX2TO1.mr23.00 B27-04-16|12:44
mux2to1_32-verilog.pvl8.80 kB27-04-16|12:44
mux2to1_32-verilog.syn287.00 B27-04-16|12:44
MUX2TO1_32.mr23.00 B27-04-16|12:44
mux2to1_8-verilog.pvl3.35 kB27-04-16|12:44
mux2to1_8-verilog.syn286.00 B27-04-16|12:44
MUX2TO1_8.mr23.00 B27-04-16|12:44
PC-verilog.pvl3.37 kB27-04-16|12:44
PC-verilog.syn277.00 B27-04-16|12:44
PC.mr23.00 B27-04-16|12:44
shift_left_logic_32-verilog.pvl4.17 kB27-04-16|12:44
shift_left_logic_32-verilog.syn296.00 B27-04-16|12:44
SHIFT_LEFT_LOGIC_32.mr23.00 B27-04-16|12:44
shift_right_logic_32-verilog.pvl4.17 kB27-04-16|12:44
shift_right_logic_32-verilog.syn297.00 B27-04-16|12:44
SHIFT_RIGHT_LOGIC_32.mr23.00 B27-04-16|12:44
tris-verilog.pvl1.60 kB27-04-16|12:44
tris-verilog.syn281.00 B27-04-16|12:44
TRIS.mr23.00 B27-04-16|12:44
tris_32-verilog.pvl7.41 kB27-04-16|12:44
tris_32-verilog.syn282.00 B27-04-16|12:44
TRIS_32.mr23.00 B27-04-16|12:44
xnor_32-verilog.pvl1.73 kB27-04-16|12:44
xnor_32-verilog.syn284.00 B27-04-16|12:44
XNOR_32.mr23.00 B27-04-16|12:44
.routing_guide.rgf28.08 kB25-04-16|13:23
.tmp.cfp4.50 kB25-04-16|13:23
area.final131.00 B25-04-16|13:24
cell.rep340.80 kB25-04-16|14:40
code.hex181.00 B23-04-16|19:08
command.log174.10 kB25-04-16|14:40
compile_dc.tcl2.59 kB25-04-16|13:08
compile_dc.tcl~2.59 kB25-04-16|13:00
cpu32.conn.rpt496.00 B25-04-16|13:24
cpu32.cts_trace17.43 kB25-04-16|13:23
cpu32.geom.rpt527.00 B25-04-16|13:24
cpu32.sdc5.06 kB25-04-16|14:40
cpu32.v17.67 kB23-04-16|19:29
cpu32.vh451.10 kB25-04-16|14:40
cpu32_modify.v~15.29 kB27-04-16|10:44
cpu32_test.v2.04 kB19-04-16|22:38
cts.rguide0.00 B25-04-16|13:23
CTS_RP_MOVE.txt346.00 B25-04-16|13:23
default.svf56.75 kB25-04-16|14:40
encounter.cmd822.00 B25-04-16|13:04
encounter.cmd12.91 kB25-04-16|13:25
encounter.conf2.71 kB25-04-16|13:11
encounter.conf~2.71 kB25-04-16|13:04
encounter.cts1.56 kB25-04-16|13:23
encounter.log3.90 kB25-04-16|13:04
encounter.log1120.65 kB25-04-16|13:25
encounter.tcl3.66 kB07-04-16|14:58
encounter.tcl.old_jan20143.47 kB07-04-16|14:58
final.dspf10.82 MB25-04-16|13:24
final.gds24.20 MB25-04-16|13:24
final.v480.75 kB25-04-16|13:24
fm_shell_command.log1.84 kB25-04-16|13:27
formality.log13.71 kB25-04-16|13:26
gds2_encounter.map2.08 kB07-04-16|14:58
gds2_virtuoso.map1.20 kB07-04-16|14:58
gscl45nm.v21.99 kB07-04-16|14:58
ipo1.txt356.00 B25-04-16|13:23
ipo2.txt356.00 B25-04-16|13:24
libManager.log813.00 B25-04-16|13:29
power.final3.92 kB25-04-16|13:24
power.rep2.14 kB25-04-16|14:40
report.ctsmdl101.00 B25-04-16|13:23
report.ctsrpt44.45 kB25-04-16|13:23
report.post_troute.ctsrpt44.36 kB25-04-16|13:23
shm.dsn521.70 kB27-04-16|11:41
shm.trn1.86 MB27-04-16|11:41
skew.post_troute_local.ctsrpt44.54 kB25-04-16|13:23
timing.rep7.30 kB25-04-16|14:40
timing.rep.1.placed232.14 kB25-04-16|13:23
timing.rep.2.ipo1232.14 kB25-04-16|13:23
timing.rep.3.cts231.92 kB25-04-16|13:24
timing.rep.4.ipo2180.75 kB25-04-16|13:24
timing.rep.5.final181.26 kB25-04-16|13:24
verilog.log14.66 kB27-04-16|11:41
adder-verilog.pvl2.62 kB25-04-16|14:38
adder-verilog.syn280.00 B25-04-16|14:38
ADDER.mr23.00 B25-04-16|14:38
adder1-verilog.pvl2.85 kB25-04-16|14:38
adder1-verilog.syn283.00 B25-04-16|14:38
ADDER1.mr23.00 B25-04-16|14:38
adder4-verilog.pvl3.63 kB25-04-16|14:38
adder4-verilog.syn281.00 B25-04-16|14:38
ADDER4.mr23.00 B25-04-16|14:38
adder_32-verilog.pvl4.73 kB25-04-16|14:38
adder_32-verilog.syn285.00 B25-04-16|14:38
ADDER_32.mr23.00 B25-04-16|14:38
addsub_32-verilog.pvl7.86 kB25-04-16|14:38
addsub_32-verilog.syn286.00 B25-04-16|14:38
ADDSUB_32.mr23.00 B25-04-16|14:38
alu_32-verilog.pvl4.99 kB25-04-16|14:38
alu_32-verilog.syn283.00 B25-04-16|14:38
ALU_32.mr23.00 B25-04-16|14:38
and_32-verilog.pvl1.72 kB25-04-16|14:38
and_32-verilog.syn281.00 B25-04-16|14:38
AND_32.mr23.00 B25-04-16|14:38
control-verilog.pvl5.92 kB25-04-16|14:38
control-verilog.syn284.00 B25-04-16|14:38
CONTROL.mr23.00 B25-04-16|14:38
cpu32-verilog.pvl6.95 kB25-04-16|14:38
cpu32-verilog.syn280.00 B25-04-16|14:38
CPU32.mr23.00 B25-04-16|14:38
decoder2to4-verilog.pvl2.71 kB25-04-16|14:38
decoder2to4-verilog.syn288.00 B25-04-16|14:38
DECODER2TO4.mr23.00 B25-04-16|14:38
decoder3to8-verilog.pvl2.61 kB25-04-16|14:38
decoder3to8-verilog.syn288.00 B25-04-16|14:38
DECODER3TO8.mr23.00 B25-04-16|14:38
decoder4to16-verilog.pvl2.61 kB25-04-16|14:38
decoder4to16-verilog.syn289.00 B25-04-16|14:38
DECODER4TO16.mr23.00 B25-04-16|14:38
dff-verilog.pvl1.54 kB25-04-16|14:38
dff-verilog.syn280.00 B25-04-16|14:38
DFF.mr23.00 B25-04-16|14:38
dff_32-verilog.pvl7.40 kB25-04-16|14:38
dff_32-verilog.syn283.00 B25-04-16|14:38
DFF_32.mr23.00 B25-04-16|14:38
dff_8-verilog.pvl2.94 kB25-04-16|14:38
dff_8-verilog.syn280.00 B25-04-16|14:38
DFF_8.mr23.00 B25-04-16|14:38
inc_8-verilog.pvl4.02 kB25-04-16|14:38
inc_8-verilog.syn282.00 B25-04-16|14:38
INC_8.mr23.00 B25-04-16|14:38
memory16_32-verilog.pvl7.35 kB25-04-16|14:38
memory16_32-verilog.syn288.00 B25-04-16|14:38
MEMORY16_32.mr23.00 B25-04-16|14:38
memory_32-verilog.pvl2.88 kB25-04-16|14:38
memory_32-verilog.syn286.00 B25-04-16|14:38
MEMORY_32.mr23.00 B25-04-16|14:38
mux2to1-verilog.pvl2.33 kB25-04-16|14:38
mux2to1-verilog.syn282.00 B25-04-16|14:38
MUX2TO1.mr23.00 B25-04-16|14:38
mux2to1_32-verilog.pvl8.80 kB25-04-16|14:38
mux2to1_32-verilog.syn287.00 B25-04-16|14:38
MUX2TO1_32.mr23.00 B25-04-16|14:38
mux2to1_8-verilog.pvl3.35 kB25-04-16|14:38
mux2to1_8-verilog.syn286.00 B25-04-16|14:38
MUX2TO1_8.mr23.00 B25-04-16|14:38
PC-verilog.pvl3.37 kB25-04-16|14:38
PC-verilog.syn277.00 B25-04-16|14:38
PC.mr23.00 B25-04-16|14:38
shift_left_logic_32-verilog.pvl4.17 kB25-04-16|14:38
shift_left_logic_32-verilog.syn296.00 B25-04-16|14:38
SHIFT_LEFT_LOGIC_32.mr23.00 B25-04-16|14:38
shift_right_logic_32-verilog.pvl4.17 kB25-04-16|14:38
shift_right_logic_32-verilog.syn295.00 B25-04-16|14:38
SHIFT_RIGHT_LOGIC_32.mr23.00 B25-04-16|14:38
tris-verilog.pvl1.60 kB25-04-16|14:38
tris-verilog.syn281.00 B25-04-16|14:38
TRIS.mr23.00 B25-04-16|14:38
tris_32-verilog.pvl7.41 kB25-04-16|14:38
tris_32-verilog.syn282.00 B25-04-16|14:38
TRIS_32.mr23.00 B25-04-16|14:38
xnor_32-verilog.pvl1.73 kB25-04-16|14:38
xnor_32-verilog.syn284.00 B25-04-16|14:38
XNOR_32.mr23.00 B25-04-16|14:38
GTECH_COMPONENTS.pbd0.00 B28-04-16|14:14
GTECH_COMPONENTS.pbd0.00 B28-04-16|14:14
AND2X1.mod0.00 B28-04-16|14:14
AND2X2.mod0.00 B28-04-16|14:14
AOI21X1.mod0.00 B28-04-16|14:14
AOI22X1.mod0.00 B28-04-16|14:14
BUFX2.mod0.00 B28-04-16|14:14
BUFX4.mod0.00 B28-04-16|14:14
CLKBUF1.mod0.00 B28-04-16|14:14
CLKBUF2.mod0.00 B28-04-16|14:14
CLKBUF3.mod0.00 B28-04-16|14:14
DFFNEGX1.mod0.00 B28-04-16|14:14
DFFPOSX1.mod0.00 B28-04-16|14:14
DFFSR.mod0.00 B28-04-16|14:14
FAX1.mod0.00 B28-04-16|14:14
HAX1.mod0.00 B28-04-16|14:14
INVX1.mod0.00 B28-04-16|14:14
INVX2.mod0.00 B28-04-16|14:14
INVX4.mod0.00 B28-04-16|14:14
INVX8.mod0.00 B28-04-16|14:14
LATCH.mod0.00 B28-04-16|14:14
MUX2X1.mod0.00 B28-04-16|14:14
NAND2X1.mod0.00 B28-04-16|14:14
NAND3X1.mod0.00 B28-04-16|14:14
NOR2X1.mod0.00 B28-04-16|14:14
NOR3X1.mod0.00 B28-04-16|14:14
OAI21X1.mod0.00 B28-04-16|14:14
OAI22X1.mod0.00 B28-04-16|14:14
OR2X1.mod0.00 B28-04-16|14:14
OR2X2.mod0.00 B28-04-16|14:14
TBUFX1.mod0.00 B28-04-16|14:14
TBUFX2.mod0.00 B28-04-16|14:14
udp_dff.udp0.00 B28-04-16|14:14
udp_mux2.udp0.00 B28-04-16|14:14
udp_rslat.udp0.00 B28-04-16|14:14
udp_tlat.udp0.00 B28-04-16|14:14
XNOR2X1.mod0.00 B28-04-16|14:14
XOR2X1.mod0.00 B28-04-16|14:14
adder.mod0.00 B28-04-16|14:14
adder_32.mod0.00 B28-04-16|14:14
addsub_32.mod0.00 B28-04-16|14:14
alu_32.mod0.00 B28-04-16|14:14
and_32.mod0.00 B28-04-16|14:14
compare_32.mod0.00 B28-04-16|14:14
control.mod0.00 B28-04-16|14:14
cpu32.mod0.00 B28-04-16|14:14
decoder2to4.mod0.00 B28-04-16|14:14
decoder3to8.mod0.00 B28-04-16|14:14
decoder4to16.mod0.00 B28-04-16|14:14
dff.mod0.00 B28-04-16|14:14
dff_32.mod0.00 B28-04-16|14:14
dff_8.mod0.00 B28-04-16|14:14
inc_8.mod0.00 B28-04-16|14:14
memory16_32.mod0.00 B28-04-16|14:14
memory_32.mod0.00 B28-04-16|14:14
mux2to1.mod0.00 B28-04-16|14:14
mux2to1_32.mod0.00 B28-04-16|14:14
mux2to1_8.mod0.00 B28-04-16|14:14
PC.mod0.00 B28-04-16|14:14
shift_left_logic_32.mod0.00 B28-04-16|14:14
shift_right_logic_32.mod0.00 B28-04-16|14:14
tris.mod0.00 B28-04-16|14:14
tris_32.mod0.00 B28-04-16|14:14
xnor_32.mod0.00 B28-04-16|14:14
GTECH_COMPONENTS.pbd0.00 B28-04-16|14:14
AND2X1.mod0.00 B28-04-16|14:14
AND2X2.mod0.00 B28-04-16|14:14
AOI21X1.mod0.00 B28-04-16|14:14
AOI22X1.mod0.00 B28-04-16|14:14
BUFX2.mod0.00 B28-04-16|14:14
BUFX4.mod0.00 B28-04-16|14:14
CLKBUF1.mod0.00 B28-04-16|14:14
CLKBUF2.mod0.00 B28-04-16|14:14
CLKBUF3.mod0.00 B28-04-16|14:14
DFFNEGX1.mod0.00 B28-04-16|14:14
DFFPOSX1.mod0.00 B28-04-16|14:14
DFFSR.mod0.00 B28-04-16|14:14
FAX1.mod0.00 B28-04-16|14:14
HAX1.mod0.00 B28-04-16|14:14
INVX1.mod0.00 B28-04-16|14:14
INVX2.mod0.00 B28-04-16|14:14
INVX4.mod0.00 B28-04-16|14:14
INVX8.mod0.00 B28-04-16|14:14
LATCH.mod0.00 B28-04-16|14:14
MUX2X1.mod0.00 B28-04-16|14:14
NAND2X1.mod0.00 B28-04-16|14:14
NAND3X1.mod0.00 B28-04-16|14:14
NOR2X1.mod0.00 B28-04-16|14:14
NOR3X1.mod0.00 B28-04-16|14:14
OAI21X1.mod0.00 B28-04-16|14:14
OAI22X1.mod0.00 B28-04-16|14:14
OR2X1.mod0.00 B28-04-16|14:14
OR2X2.mod0.00 B28-04-16|14:14
TBUFX1.mod0.00 B28-04-16|14:14
TBUFX2.mod0.00 B28-04-16|14:14
udp_dff.udp0.00 B28-04-16|14:14
udp_mux2.udp0.00 B28-04-16|14:14
udp_rslat.udp0.00 B28-04-16|14:14
udp_tlat.udp0.00 B28-04-16|14:14
XNOR2X1.mod0.00 B28-04-16|14:14
XOR2X1.mod0.00 B28-04-16|14:14
adder.mod0.00 B28-04-16|14:14
adder_32.mod0.00 B28-04-16|14:14
addsub_32.mod0.00 B28-04-16|14:14
alu_32.mod0.00 B28-04-16|14:14
and_32.mod0.00 B28-04-16|14:14
compare_32.mod0.00 B28-04-16|14:14
control.mod0.00 B28-04-16|14:14
cpu32.mod0.00 B28-04-16|14:14
decoder2to4.mod0.00 B28-04-16|14:14
decoder3to8.mod0.00 B28-04-16|14:14
decoder4to16.mod0.00 B28-04-16|14:14
dff.mod0.00 B28-04-16|14:14
dff_32.mod0.00 B28-04-16|14:14
dff_8.mod0.00 B28-04-16|14:14
inc_8.mod0.00 B28-04-16|14:14
memory16_32.mod0.00 B28-04-16|14:14
memory_32.mod0.00 B28-04-16|14:14
mux2to1.mod0.00 B28-04-16|14:14
mux2to1_32.mod0.00 B28-04-16|14:14
mux2to1_8.mod0.00 B28-04-16|14:14
PC.mod0.00 B28-04-16|14:14
shift_left_logic_32.mod0.00 B28-04-16|14:14
shift_right_logic_32.mod0.00 B28-04-16|14:14
tris.mod0.00 B28-04-16|14:14
tris_32.mod0.00 B28-04-16|14:14
xnor_32.mod0.00 B28-04-16|14:14
GTECH_COMPONENTS.pbd0.00 B28-04-16|14:14
AND2X1.mod0.00 B28-04-16|14:14
AND2X2.mod0.00 B28-04-16|14:14
AOI21X1.mod0.00 B28-04-16|14:14
AOI22X1.mod0.00 B28-04-16|14:14
BUFX2.mod0.00 B28-04-16|14:14
BUFX4.mod0.00 B28-04-16|14:14
CLKBUF1.mod0.00 B28-04-16|14:14
CLKBUF2.mod0.00 B28-04-16|14:14
CLKBUF3.mod0.00 B28-04-16|14:14
DFFNEGX1.mod0.00 B28-04-16|14:14
DFFPOSX1.mod0.00 B28-04-16|14:14
DFFSR.mod0.00 B28-04-16|14:14
FAX1.mod0.00 B28-04-16|14:14
HAX1.mod0.00 B28-04-16|14:14
INVX1.mod0.00 B28-04-16|14:14
INVX2.mod0.00 B28-04-16|14:14
INVX4.mod0.00 B28-04-16|14:14
INVX8.mod0.00 B28-04-16|14:14
LATCH.mod0.00 B28-04-16|14:14
MUX2X1.mod0.00 B28-04-16|14:14
NAND2X1.mod0.00 B28-04-16|14:14
NAND3X1.mod0.00 B28-04-16|14:14
NOR2X1.mod0.00 B28-04-16|14:14
NOR3X1.mod0.00 B28-04-16|14:14
OAI21X1.mod0.00 B28-04-16|14:14
OAI22X1.mod0.00 B28-04-16|14:14
OR2X1.mod0.00 B28-04-16|14:14
OR2X2.mod0.00 B28-04-16|14:14
TBUFX1.mod0.00 B28-04-16|14:14
TBUFX2.mod0.00 B28-04-16|14:14
udp_dff.udp0.00 B28-04-16|14:14
udp_mux2.udp0.00 B28-04-16|14:14
udp_rslat.udp0.00 B28-04-16|14:14
udp_tlat.udp0.00 B28-04-16|14:14
XNOR2X1.mod0.00 B28-04-16|14:14
XOR2X1.mod0.00 B28-04-16|14:14
adder.mod0.00 B28-04-16|14:14
adder_32.mod0.00 B28-04-16|14:14
addsub_32.mod0.00 B28-04-16|14:14
alu_32.mod0.00 B28-04-16|14:14
and_32.mod0.00 B28-04-16|14:14
compare_32.mod0.00 B28-04-16|14:14
control.mod0.00 B28-04-16|14:14
cpu32.mod0.00 B28-04-16|14:14
decoder2to4.mod0.00 B28-04-16|14:14
decoder3to8.mod0.00 B28-04-16|14:14
decoder4to16.mod0.00 B28-04-16|14:14
dff.mod0.00 B28-04-16|14:14
dff_32.mod0.00 B28-04-16|14:14
dff_8.mod0.00 B28-04-16|14:14
inc_8.mod0.00 B28-04-16|14:14
memory16_32.mod0.00 B28-04-16|14:14
memory_32.mod0.00 B28-04-16|14:14
mux2to1.mod0.00 B28-04-16|14:14
mux2to1_32.mod0.00 B28-04-16|14:14
mux2to1_8.mod0.00 B28-04-16|14:14
PC.mod0.00 B28-04-16|14:14
shift_left_logic_32.mod0.00 B28-04-16|14:14
shift_right_logic_32.mod0.00 B28-04-16|14:14
tris.mod0.00 B28-04-16|14:14
tris_32.mod0.00 B28-04-16|14:14
xnor_32.mod0.00 B28-04-16|14:14
workspaces0.00 B28-04-16|14:14
GTECH_COMPONENTS.pkg0.00 B28-04-16|14:14
GTECH_COMPONENTS.pkg0.00 B28-04-16|14:14
TECH_WORK0.00 B28-04-16|14:14
WORK0.00 B28-04-16|14:14
WORK0.00 B28-04-16|14:14
GTECH_COMPONENTS.pkg0.00 B28-04-16|14:14
TECH_WORK0.00 B28-04-16|14:14
WORK0.00 B28-04-16|14:14
WORK0.00 B28-04-16|14:14
GTECH_COMPONENTS.pkg0.00 B28-04-16|14:14
TECH_WORK0.00 B28-04-16|14:14
WORK0.00 B28-04-16|14:14
WORK0.00 B28-04-16|14:14
viva0.00 B28-04-16|14:15
workspaces0.00 B28-04-16|14:15
edi0.00 B28-04-16|14:14
GTECH0.00 B28-04-16|14:14
i0.00 B28-04-16|14:14
r0.00 B28-04-16|14:14
server0.00 B28-04-16|14:14
GTECH0.00 B28-04-16|14:14
i0.00 B28-04-16|14:14
r0.00 B28-04-16|14:14
server0.00 B28-04-16|14:14
GTECH0.00 B28-04-16|14:14
i0.00 B28-04-16|14:14
r0.00 B28-04-16|14:14
server0.00 B28-04-16|14:14
GTECH0.00 B28-04-16|14:14
i0.00 B28-04-16|14:14
r0.00 B28-04-16|14:14
server0.00 B28-04-16|14:14
dfII0.00 B28-04-16|14:15
edi0.00 B28-04-16|14:15
.cadence0.00 B28-04-16|14:14
.simvision0.00 B28-04-16|14:14
FM_WORK0.00 B28-04-16|14:14
FM_WORK10.00 B28-04-16|14:14
FM_WORK20.00 B28-04-16|14:14
FM_WORK30.00 B28-04-16|14:14
shm.db0.00 B28-04-16|14:15
WORK0.00 B28-04-16|14:14
.cadence0.00 B28-04-16|14:15
shm.db0.00 B28-04-16|14:15
WORK0.00 B28-04-16|14:15
carry_ripple0.00 B28-04-16|14:15
carry_skip0.00 B28-04-16|14:15
code.hex67.00 B03-05-16|20:58
cpu32_cmp.v18.17 kB24-04-16|17:36
cpu32_test.v2.04 kB19-04-16|22:38
bonus0.00 B03-05-16|20:56
...
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cpu32_cmp.v (9.83 MB)

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