escalator_tb.v ( File view )

  • By rajaram431 2016-04-21
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			`timescale 1ns / 1ps

// Company: 
// Engineer:
// Create Date:   15:17:09 05/18/2012
// Design Name:   escalator
// Module Name:   C:/Documents and Settings/siva/Desktop/mini_final/18-5-12/escalator/escalator_tb.v
// Project Name:  escalator
// Target Device:  
// Tool versions:  
// Description: 
// Verilog Test Fixture created by ISE for module: escalator
// Dependencies:
// Revision:
// Revision 0.01 - File Created
// Additional Comments:

module escalator_tb_v;

	// Inputs
	reg clk;
	reg rst;
	reg upsensor;
	reg downsensor;

	// Outputs
	wire up;
	wire down;
	wire hold1;
	wire hold2;
 //integer i;

	// Instantiate the Unit Under Test (UUT)
	escalator uut (
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File list

Tips: You can preview the content of files by clicking file names^_^
Name Size Date
code.exe813.00 kB25-09-10|11:00
elevator.exe813.00 kB25-09-10|11:00
elevator.v2.29 kB22-05-12|16:49
elevator_tb.v1.37 kB22-05-12|17:00
eleva_tb.v1.43 kB22-05-12|16:56
escalator.exe813.00 kB25-09-10|11:00
escalator.v1.00 kB11-07-13|17:35
escalator_tb.v1.42 kB18-05-12|15:23
elevator0.00 B06-01-15|17:14
escalator0.00 B21-04-16|10:29
code0.00 B21-04-16|10:29
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escalator_tb.v (889.63 kB)

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