eleva_tb.v ( File view )

  • By rajaram431 2016-04-21
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			`timescale 1ns / 1ps

// Company: 
// Engineer:
// Create Date:   10:33:53 05/11/2012
// Design Name:   elevator
// Module Name:   C:/Xilinx92i/siva/miniverilog/completed/elevator/eleva_tb.v
// Project Name:  elevator
// Target Device:  
// Tool versions:  
// Description: 
// Verilog Test Fixture created by ISE for module: elevator
// Dependencies:
// Revision:
// Revision 0.01 - File Created
// Additional Comments:

module eleva_tb_v;

	// Inputs
	reg clk;
	reg rst;
	reg [1:0] datain;

	// Outputs
	wire out0;
	wire out1;
	wire out2;
	wire out3;
	wire door_open,door_open1,door_open2,door_open3;
	integer i;

	// Instantiate the Unit Under Test (UUT)
	elevator uut (
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File list

Tips: You can preview the content of files by clicking file names^_^
Name Size Date
code.exe813.00 kB25-09-10|11:00
elevator.exe813.00 kB25-09-10|11:00
elevator.v2.29 kB22-05-12|16:49
elevator_tb.v1.37 kB22-05-12|17:00
eleva_tb.v1.43 kB22-05-12|16:56
escalator.exe813.00 kB25-09-10|11:00
escalator.v1.00 kB11-07-13|17:35
escalator_tb.v1.42 kB18-05-12|15:23
elevator0.00 B06-01-15|17:14
escalator0.00 B21-04-16|10:29
code0.00 B21-04-16|10:29
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eleva_tb.v (889.63 kB)

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