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XLINX V5 Chip DDR SDRAM reference design

2016-07-26 00:24:03
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HDL design files
  \sim   - simulation files
  \synth - Synthesis related files
  \par   - Place/Route related files

以及DDR SDRAM控制器设置.pdf文件

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File list

Tips: You can preview the content of files by clicking file names^_^
Name Size Date
DDR0.00 B67%|26-07-16
hwtb_ddr1_top.ucf17.37 kB11-05-06|16:31
readme.txt8.67 kB20-07-06|11:22
CLK_module.vhd4.31 kB10-05-06|14:01
ddr1_backend_fifos.vhd4.43 kB11-05-06|16:11
ddr1_controller.vhd37.48 kB20-07-06|11:21
ddr1_parameters.vhd6.73 kB11-05-06|19:09
ddr1_rd_wr_addr_fifo.vhd3.66 kB10-05-06|19:52
ddr1_top.vhd8.75 kB11-05-06|15:43
ddr1_wr_data_fifo_16.vhd2.87 kB10-05-06|19:52
hwtb_ddr1_top.vhd13.30 kB11-05-06|16:01
phy_adr_out.vhd2.17 kB10-05-06|14:02
phy_ctrl_out.vhd3.01 kB11-05-06|15:37
phy_data_read.vhd3.54 kB10-05-06|14:02
phy_data_write.vhd4.93 kB10-05-06|14:03
phy_dq_align.vhd11.06 kB10-05-06|14:03
phy_init.vhd9.07 kB10-05-06|14:03
phy_ptn_gen.vhd13.68 kB10-05-06|14:03
phy_rden_align.vhd7.74 kB10-05-06|14:03
phy_top.vhd19.63 kB11-05-06|15:19
PKG_PRBS.vhd75.35 kB10-05-06|14:03
ddr.v55.59 kB05-08-05|10:24
ddr_parameters.vh8.69 kB05-08-05|10:24
do_hwtb_ddr1_top.do2.58 kB11-05-06|14:53
tb_HWTB_ddr1_top.vhd5.49 kB11-05-06|16:04
wv_hwtb_ddr1_top.do51.56 kB11-05-06|14:48
hwtb_ddr1_top.prj3.14 kB10-05-06|14:26
hwtb_ddr1_top.sdc2.48 kB11-05-06|16:23
par0.00 B20-07-06|11:19
rtl0.00 B20-07-06|11:21
sim0.00 B20-07-06|11:19
synth0.00 B20-07-06|11:19
xapp8510.00 B26-07-16|11:43
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XLINX V5 Chip DDR SDRAM reference design (452.17 kB)

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