Home » Source Code » Use Verilog HDL to realize common UART serial communications procedures, proven success

Use Verilog HDL to realize common UART serial communications procedures, proven success

2016-05-31 03:07:29
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In the ISE General serial communication program developed by using programming language is the Verilog HDL language, using a FIFO, experiments have been carried out by suitable for Verilog beginners, welcomed the exchange of learning.
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Name Size Date
fifo_uart.bsf3.01 kB24-03-11|15:46
fifo_uart.qip366.00 B24-03-11|15:46
fifo_uart.v6.52 kB24-03-11|15:46
fifo_uart_bb.v5.47 kB24-03-11|15:46
fifo_uart_wave0.jpg77.00 kB24-03-11|15:46
fifo_uart_wave1.jpg69.88 kB24-03-11|15:46
fifo_uart_waveforms.html1.07 kB24-03-11|15:46
uart_fifo_design.asm.rpt8.37 kB29-06-11|15:29
uart_fifo_design.cdf358.00 B29-06-11|15:32
uart_fifo_design.done26.00 B29-06-11|15:29
uart_fifo_design.dpf239.00 B29-06-11|15:28
uart_fifo_design.fit.rpt196.04 kB29-06-11|15:29
uart_fifo_design.fit.smsg513.00 B29-06-11|15:29
uart_fifo_design.fit.summary634.00 B29-06-11|15:29
uart_fifo_design.flow.rpt8.93 kB29-06-11|15:29
uart_fifo_design.map.rpt53.70 kB29-06-11|15:29
uart_fifo_design.map.summary486.00 B29-06-11|15:29
uart_fifo_design.pin77.14 kB29-06-11|15:29
uart_fifo_design.pof512.20 kB29-06-11|15:29
uart_fifo_design.qpf1.26 kB24-03-11|15:21
uart_fifo_design.qsf4.14 kB29-06-11|15:28
uart_fifo_design.qws591.00 B29-06-11|15:35
uart_fifo_design.sim.rpt168.46 kB24-03-11|15:22
uart_fifo_design.sof821.39 kB29-06-11|15:29
uart_fifo_design.sta.rpt345.42 kB24-03-11|15:22
uart_fifo_design.sta.summary923.00 B24-03-11|15:22
uart_fifo_design.tan.rpt252.08 kB29-06-11|15:29
uart_fifo_design.tan.summary2.04 kB29-06-11|15:29
uart_fifo_design.tcl4.14 kB29-06-11|15:28
uart_fifo_design.tcl.bak3.95 kB29-06-11|15:27
uart_fifo_design.vwf11.41 kB24-03-11|15:22
clk_generator.v2.87 kB24-03-11|16:31
clk_generator.v.bak2.84 kB24-03-11|16:31
fifo_read_write.v2.08 kB24-03-11|15:40
fifo_read_write.v.bak2.08 kB24-03-11|15:22
key_scan.v1.79 kB24-03-11|15:37
key_scan.v.bak1.67 kB24-03-11|15:22
system_ctrl.v1.00 kB24-03-11|15:22
system_ctrl.v.bak1.00 kB24-03-11|15:22
transcript128.00 B24-03-11|15:22
uart_fifo_design.v1.54 kB29-06-11|15:26
uart_fifo_design.v.bak1.52 kB24-03-11|15:40
uart_receiver.v2.46 kB24-03-11|15:22
uart_receiver.v.bak2.46 kB24-03-11|15:22
uart_transfer.v2.00 kB24-03-11|15:22
uart_transfer.v.bak2.00 kB24-03-11|15:22
src0.00 B08-08-11|12:03
uart_fifo_design0.00 B08-08-11|12:03
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Use Verilog HDL to realize common UART serial communications procedures, proven success (178.11 kB)

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