# $Id: 自述,2005年-12-06 v1.1.1.1 2:47:45 Exp $ arif_endro目录布局.| — — 板凳-> 测试 benchdirectory|| — — 数据-> 数据 files,'ecb_tbl.txt\' 用于核查文件。||-doc-> documentationfiles|' — — 源-> VHDL 源代...">
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mini_aes verilog code in xilinx ise design suite

2015-04-20 14:26:31
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size:16px;"># $Id: 自述,2005年-12-06 v1.1.1.1 2:47:45 Exp $ arif_endro


| — — 板凳-> 测试 benchdirectory
| — — 数据-> 数据 files,'ecb_tbl.txt\' 用于核查文件。
|-doc-> documentationfiles
' — — 源-> VHDL 源代码的这个项目。


然后运行协同文件,即 'modelsim_bench.do\'。这种模拟
将生成输出到一个文件中被称为 'ecb_tbl_result_enc.txt\' 和


Arif E.努格罗霍
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Name Size Date
0.00 B2013-02-20|20:45
0.00 B2013-02-20|20:45
0.00 B2013-02-20|20:45
0.00 B2013-02-20|20:45
0.00 B2013-02-20|20:45
aes.pdf815.03 kB2013-02-20|20:43
0.00 B2013-02-20|20:45
test_table_lookup.v1.36 kB2012-10-14|06:02
test_aes_256.v1.85 kB2012-10-20|01:21
test_aes_192.v1.81 kB2012-10-20|01:21
test_aes_128.v2.31 kB2012-10-20|01:21
simulation.do424.00 B2012-10-14|07:02
Read_Me.txt527.00 B2012-10-14|07:02
test_endian.v866.00 B2012-10-14|06:02
0.00 B2013-02-20|20:45
0.00 B2013-02-20|20:45
constraints.ucf10.55 kB2012-10-20|00:50
0.00 B2013-02-20|20:45
README124.00 B2013-01-07|22:14
gen_test_case.c2.58 kB2013-01-07|22:14
sbox.h4.23 kB2013-01-07|22:14
aes.c11.29 kB2013-01-07|22:14
LICENSE11.09 kB2012-10-14|06:02
0.00 B2013-02-20|20:45
aes_192.v5.87 kB2012-10-16|07:20
aes_128.v2.62 kB2012-10-16|07:20
aes_256.v4.37 kB2012-10-16|07:20
round.v2.58 kB2012-10-16|07:20
table.v14.40 kB2012-10-16|07:20
NOTICE573.00 B2012-10-14|06:02
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