Home » Source Code » UART RING FPGA BASYS 2

UART RING FPGA BASYS 2

eecc
2014-11-25 21:14:55
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WindowsWindows Verilog HDLVerilog

Description

This is a proyect made in verilog sours code, the proyect is about of transmit byts from one basys to another 3 basys with a protocol of tranmition and receptions of bytes
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File list

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Name Size Date
decod.v642.00 B09-05-14|13:36
enviar.v2.43 kB09-05-14|13:36
gtv1.v262.00 B09-05-14|13:36
gtv2.v253.00 B09-05-14|13:36
toplevel.xreport20.07 kB10-11-14|08:57
UARTRing.projectmgr5.59 kB05-11-14|12:52
mux4a1.v360.00 B10-11-14|09:22
receptor.v1.38 kB09-05-14|13:36
reloj.v526.00 B09-05-14|13:36
toplevel.bgn4.59 kB10-11-14|09:23
toplevel.bit71.06 kB10-11-14|09:23
toplevel.bld1,016.00 B10-11-14|09:22
toplevel.cmd_log31.42 kB10-11-14|09:22
toplevel.drc192.00 B10-11-14|09:23
toplevel.lso6.00 B10-11-14|09:22
toplevel.ncd74.83 kB10-11-14|09:22
toplevel.ngc105.78 kB10-11-14|09:22
toplevel.ngd160.32 kB10-11-14|09:22
toplevel.ngr94.16 kB10-11-14|09:22
toplevel.pad6.92 kB10-11-14|09:22
toplevel.par7.95 kB10-11-14|09:22
toplevel.pcf1.72 kB10-11-14|09:22
toplevel.prj257.00 B10-11-14|09:22
toplevel.ptwx17.09 kB10-11-14|09:22
toplevel.stx0.00 B10-11-14|09:22
toplevel.syr27.87 kB10-11-14|09:22
toplevel.twr3.40 kB10-11-14|09:22
toplevel.twx20.82 kB10-11-14|09:22
toplevel.ucf1.35 kB05-11-14|12:42
toplevel.unroutes159.00 B10-11-14|09:22
toplevel.ut393.00 B10-11-14|09:22
toplevel.v1.81 kB05-11-14|12:42
toplevel.xpi46.00 B10-11-14|09:22
toplevel.xst1.12 kB10-11-14|09:22
toplevel_bitgen.xwbt221.00 B10-11-14|09:23
toplevel_envsettings.html13.21 kB10-11-14|08:57
toplevel_guide.ncd74.83 kB10-11-14|09:22
toplevel_map.map2.58 kB10-11-14|09:22
toplevel_map.mrp10.02 kB10-11-14|09:22
toplevel_map.ncd49.18 kB10-11-14|09:22
toplevel_map.ngm285.77 kB10-11-14|09:22
toplevel_map.xrpt23.49 kB10-11-14|09:22
toplevel_ngdbuild.xrpt7.82 kB10-11-14|09:22
toplevel_pad.csv6.95 kB10-11-14|09:22
toplevel_pad.txt26.55 kB10-11-14|09:22
toplevel_par.xrpt76.50 kB10-11-14|09:22
toplevel_summary.html8.77 kB10-11-14|08:57
toplevel_summary.xml409.00 B10-11-14|09:23
toplevel_usage.xml17.22 kB10-11-14|09:23
toplevel_xst.xrpt14.05 kB10-11-14|09:22
transistor.v344.00 B09-05-14|13:36
UARTControl.v1.73 kB09-05-14|13:36
UARTRing.gise11.82 kB10-11-14|09:23
UARTRing.xise35.22 kB04-11-14|17:02
usage_statistics_webtalk.html82.16 kB10-11-14|09:23
webtalk.log714.00 B10-11-14|09:23
webtalk_pn.xml2.94 kB10-11-14|09:22
cst.xbcd3.16 kB10-11-14|09:22
hdllib.ref564.00 B10-11-14|09:22
gtv1.bin1.31 kB10-11-14|09:22
gtv2.bin1.31 kB10-11-14|09:22
transistor.bin1.88 kB10-11-14|09:22
decod.bin4.06 kB10-11-14|09:22
reloj.bin1.32 kB10-11-14|09:22
receptor.bin4.95 kB10-11-14|09:22
toplevel.bin6.69 kB10-11-14|09:22
_u_a_r_t_control.bin6.50 kB10-11-14|09:22
transmisor.bin6.62 kB10-11-14|09:22
mux4a1.bin2.93 kB10-11-14|09:22
netlist.lst51.00 B10-11-14|09:22
bitgen.xmsgs367.00 B10-11-14|09:23
map.xmsgs741.00 B10-11-14|09:22
ngdbuild.xmsgs367.00 B10-11-14|09:22
par.xmsgs1.41 kB10-11-14|09:22
pn_parser.xmsgs746.00 B10-11-14|09:22
trce.xmsgs1.68 kB10-11-14|09:22
xst.xmsgs1.48 kB10-11-14|09:22
notopt0.00 B29-04-14|20:56
opt0.00 B29-04-14|20:56
ngx0.00 B09-05-14|13:36
toplevel.prj0.00 B09-05-14|13:36
vlg1E0.00 B09-05-14|13:36
vlg1F0.00 B09-05-14|13:36
vlg210.00 B09-05-14|13:36
vlg2F0.00 B09-05-14|13:36
vlg440.00 B09-05-14|13:36
vlg4C0.00 B09-05-14|13:36
vlg630.00 B09-05-14|13:36
vlg690.00 B09-05-14|13:36
vlg6A0.00 B09-05-14|13:36
vlg780.00 B09-05-14|13:36
dump.xst0.00 B09-05-14|13:36
projnav.tmp0.00 B10-11-14|09:22
work0.00 B09-05-14|13:36
iseconfig0.00 B09-05-14|13:36
xlnx_auto_0_xdb0.00 B10-11-14|09:22
xst0.00 B09-05-14|13:36
_ngo0.00 B10-11-14|09:22
_xmsgs0.00 B10-11-14|09:23
UARTRing2.10 B0%|10-11-14
...
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Comments

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steve838
2019-09-23

I focus on protocol more than enough because I know it uses as a gem for me and my all working store their. The the-essays.com reviews help me out to design the protocol well and they also share their experience regarding the project which helps me a lot.

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UART RING FPGA BASYS 2 (384.54 kB)(385.21 kB)

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