Home » Source Code » AHB transfers to APB source and APB read/write verilog code

AHB transfers to APB source and APB read/write verilog code

parkershe
2014-05-24 18:59:54
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verilogverilog Verilog HDLVerilog

Description

power APB domain. The Bridge appears as a slave on AHB, 
whereas on APB, it is the master. Read and write transfers on the AHB are 
converted into corresponding transfers on the APB. As the APB is not 
pipelined, wait states are added during transfers to and from the APB when
the AHB is required to wait for the APB protocol.
The AHB to APB Bridge comprises of a state machine, which is used to control
the generation of the APB and AHB output signals, and the address decoding 
logic which is used to generate the APB peripheral select lines. 
All registers used in the system are clocked from the rising edge of the 
system clock HCLK, and use the asynchronous reset HRESETn
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File list

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Name Size Date
apb.v5.58 kB04-03-08|12:13
Ahb2Apb.v25.95 kB21-05-14|22:21
...
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Comments

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琴声悠扬1101
2017-03-16

nice

mvvsvas
2018-09-12

very helpful code and useful.The AHB to APB module consists of the AHB signals and APB signals included to form the controller part and the peripherals which include 6 of the slaves. The AHB to APB module consists of the AHB signals and APB signals included to form the controller part and the peripherals which include 6 of the slaves.

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AHB transfers to APB source and APB read/write verilog code (6.31 kB)

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