Home » Source Code » UART Verilog sorce code and Simulation code and FIFO code

UART Verilog sorce code and Simulation code and FIFO code

parkershe
2014-05-24 19:01:19
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verilogverilog Verilog HDLVerilog

Description

It is programed by verilog language and main code is UART,
The main source code are uart_receiver.v /uart_transmitter.v/lpm_mux0.v/myfifo.v.......
some wave file can help you understand more simulation information.
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File list

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Name Size Date
uart_regs_h.vwf67.25 kB12-06-04|00:03
uart_regs_pre.vwf72.74 kB31-12-04|13:53
lpm_mux0.bsf3.19 kB01-02-05|19:07
lpm_mux0.v4.49 kB01-02-05|19:07
lpm_mux0_bb.v1.60 kB01-02-05|19:07
sch_exam.bdf15.00 kB01-02-05|20:36
seriesPort.v7.44 kB26-06-03|17:06
uart_defines.v2.76 kB10-06-03|15:45
uart_receiver.v6.24 kB24-07-03|09:40
uart_regs.v14.50 kB02-04-07|15:35
uart_transmitter.v4.13 kB11-06-04|21:38
myfifo_10.v7.39 kB12-06-04|19:48
myfifo_10_bb.v1.68 kB12-06-04|19:48
myfifo_10_wave0.jpg99.86 kB12-06-04|19:48
myfifo_10_waveforms.html816.00 B12-06-04|19:48
myfifo_8.v7.37 kB12-06-04|19:50
myfifo_8_bb.v1.68 kB12-06-04|19:50
myfifo_8_wave0.jpg99.86 kB12-06-04|19:50
myfifo_8_waveforms.html810.00 B12-06-04|19:50
chip_editor.acv78.00 B14-01-05|23:31
cmp_state.ini2.00 B02-04-07|15:35
add_sub_1gh.tdf3.19 kB29-03-07|15:28
add_sub_1jh.tdf5.67 kB31-12-04|13:39
add_sub_ahh.tdf3.60 kB29-03-07|15:28
add_sub_dhh.tdf3.00 kB31-12-04|13:39
add_sub_ehh.tdf3.20 kB31-12-04|13:39
add_sub_fhh.tdf3.40 kB31-12-04|13:39
add_sub_ghh.tdf4.91 kB29-03-07|15:28
add_sub_ihh.tdf3.99 kB31-12-04|13:39
add_sub_rih.tdf4.40 kB31-12-04|13:39
add_sub_ufh.tdf2.59 kB29-03-07|15:28
altsyncram_9ic1.tdf12.91 kB02-04-07|14:28
altsyncram_apb1.tdf17.32 kB31-12-04|13:00
altsyncram_mmb1.tdf14.66 kB31-12-04|13:00
altsyncram_tkc1.tdf15.16 kB02-04-07|14:28
a_dpfifo_38s.tdf3.19 kB02-04-07|14:28
a_dpfifo_4nl.tdf3.98 kB31-12-04|13:00
a_dpfifo_c9s.tdf3.18 kB02-04-07|14:28
a_dpfifo_k6s.tdf4.19 kB29-03-07|15:28
a_dpfifo_rll.tdf3.99 kB31-12-04|13:00
a_dpfifo_t7s.tdf4.19 kB29-03-07|15:28
a_fefifo_66f.tdf3.65 kB29-03-07|15:28
a_fefifo_qve.tdf4.19 kB31-12-04|13:00
cntr_9d7.tdf3.44 kB02-04-07|14:28
cntr_re8.tdf3.40 kB02-04-07|14:28
dpram_76p.tdf2.20 kB02-04-07|14:28
dpram_81k.tdf2.72 kB31-12-04|13:00
dpram_g7p.tdf2.21 kB02-04-07|14:28
dpram_h2k.tdf2.72 kB31-12-04|13:00
scfifo_53s.tdf2.31 kB02-04-07|14:28
scfifo_90s.tdf2.32 kB29-03-07|15:28
scfifo_eaq.tdf2.87 kB31-12-04|13:00
scfifo_i1s.tdf2.32 kB29-03-07|15:28
scfifo_nbq.tdf2.87 kB31-12-04|13:00
scfifo_s1s.tdf2.31 kB02-04-07|14:28
uart_regs(0).cnf.cdb15.52 kB31-12-04|13:00
uart_regs(0).cnf.hdb2.74 kB31-12-04|13:00
uart_regs(1).cnf.cdb9.15 kB31-12-04|13:00
uart_regs(1).cnf.hdb1.25 kB31-12-04|13:00
uart_regs(10).cnf.cdb2.24 kB31-12-04|13:35
uart_regs(10).cnf.hdb625.00 B31-12-04|13:35
uart_regs(11).cnf.cdb1.07 kB31-12-04|13:00
uart_regs(11).cnf.hdb521.00 B31-12-04|13:00
uart_regs(12).cnf.cdb1.98 kB31-12-04|13:00
uart_regs(12).cnf.hdb668.00 B31-12-04|13:00
uart_regs(13).cnf.cdb13.09 kB31-12-04|13:00
uart_regs(13).cnf.hdb2.05 kB31-12-04|13:00
uart_regs(14).cnf.cdb1.43 kB31-12-04|13:00
uart_regs(14).cnf.hdb598.00 B31-12-04|13:00
uart_regs(15).cnf.cdb1.07 kB31-12-04|13:00
uart_regs(15).cnf.hdb493.00 B31-12-04|13:00
uart_regs(16).cnf.cdb1.01 kB31-12-04|13:00
uart_regs(16).cnf.hdb464.00 B31-12-04|13:00
uart_regs(17).cnf.cdb1.93 kB31-12-04|13:00
uart_regs(17).cnf.hdb603.00 B31-12-04|13:00
uart_regs(18).cnf.cdb1.01 kB31-12-04|13:00
uart_regs(18).cnf.hdb464.00 B31-12-04|13:00
uart_regs(19).cnf.cdb2.47 kB31-12-04|13:35
uart_regs(19).cnf.hdb635.00 B31-12-04|13:35
uart_regs(2).cnf.cdb1.39 kB31-12-04|13:00
uart_regs(2).cnf.hdb582.00 B31-12-04|13:00
uart_regs(20).cnf.cdb1.36 kB31-12-04|13:00
uart_regs(20).cnf.hdb521.00 B31-12-04|13:00
uart_regs(21).cnf.cdb2.36 kB31-12-04|13:00
uart_regs(21).cnf.hdb744.00 B31-12-04|13:00
uart_regs(3).cnf.cdb1.03 kB31-12-04|13:00
uart_regs(3).cnf.hdb494.00 B31-12-04|13:00
uart_regs(4).cnf.cdb1,005.00 B31-12-04|13:00
uart_regs(4).cnf.hdb460.00 B31-12-04|13:00
uart_regs(5).cnf.cdb1.87 kB31-12-04|13:00
uart_regs(5).cnf.hdb596.00 B31-12-04|13:00
uart_regs(6).cnf.cdb2.43 kB31-12-04|13:00
uart_regs(6).cnf.hdb688.00 B31-12-04|13:00
uart_regs(7).cnf.cdb1.09 kB31-12-04|13:00
uart_regs(7).cnf.hdb521.00 B31-12-04|13:00
uart_regs(8).cnf.cdb2.12 kB31-12-04|13:00
uart_regs(8).cnf.hdb668.00 B31-12-04|13:00
uart_regs(9).cnf.cdb983.00 B31-12-04|13:00
uart_regs(9).cnf.hdb465.00 B31-12-04|13:00
uart_regs-sim.vwf72.74 kB14-01-05|21:32
uart_regs.(0).cnf.cdb15.49 kB02-04-07|14:28
uart_regs.(0).cnf.hdb3.03 kB02-04-07|14:28
uart_regs.(1).cnf.cdb8.89 kB02-04-07|14:28
uart_regs.(1).cnf.hdb1.42 kB02-04-07|14:28
uart_regs.(10).cnf.cdb1.32 kB02-04-07|14:34
uart_regs.(10).cnf.hdb664.00 B02-04-07|14:34
uart_regs.(11).cnf.cdb1.91 kB02-04-07|14:28
uart_regs.(11).cnf.hdb772.00 B02-04-07|14:28
uart_regs.(12).cnf.cdb12.35 kB02-04-07|14:28
uart_regs.(12).cnf.hdb2.23 kB02-04-07|14:28
uart_regs.(13).cnf.cdb1.41 kB02-04-07|14:28
uart_regs.(13).cnf.hdb705.00 B02-04-07|14:28
uart_regs.(14).cnf.cdb1.08 kB02-04-07|14:28
uart_regs.(14).cnf.hdb550.00 B02-04-07|14:28
uart_regs.(15).cnf.cdb1.02 kB02-04-07|14:28
uart_regs.(15).cnf.hdb502.00 B02-04-07|14:28
uart_regs.(16).cnf.cdb1.84 kB02-04-07|14:28
uart_regs.(16).cnf.hdb663.00 B02-04-07|14:28
uart_regs.(17).cnf.cdb1.00 kB02-04-07|14:28
uart_regs.(17).cnf.hdb490.00 B02-04-07|14:28
uart_regs.(18).cnf.cdb1.38 kB02-04-07|14:34
uart_regs.(18).cnf.hdb689.00 B02-04-07|14:34
uart_regs.(2).cnf.cdb1.37 kB02-04-07|14:28
uart_regs.(2).cnf.hdb689.00 B02-04-07|14:28
uart_regs.(3).cnf.cdb1.04 kB02-04-07|14:28
uart_regs.(3).cnf.hdb550.00 B02-04-07|14:28
uart_regs.(4).cnf.cdb997.00 B02-04-07|14:28
uart_regs.(4).cnf.hdb501.00 B02-04-07|14:28
uart_regs.(5).cnf.cdb1.80 kB02-04-07|14:28
uart_regs.(5).cnf.hdb659.00 B02-04-07|14:28
uart_regs.(6).cnf.cdb2.52 kB02-04-07|14:28
uart_regs.(6).cnf.hdb777.00 B02-04-07|14:28
uart_regs.(7).cnf.cdb1,010.00 B02-04-07|14:28
uart_regs.(7).cnf.hdb581.00 B02-04-07|14:28
uart_regs.(8).cnf.cdb2.05 kB02-04-07|14:28
uart_regs.(8).cnf.hdb785.00 B02-04-07|14:28
uart_regs.(9).cnf.cdb975.00 B02-04-07|14:28
uart_regs.(9).cnf.hdb491.00 B02-04-07|14:28
uart_regs.asm.qmsg1.28 kB02-04-07|14:35
uart_regs.cbx.xml867.00 B02-04-07|14:34
uart_regs.cmp.cdb94.88 kB02-04-07|14:35
uart_regs.cmp.hdb23.31 kB02-04-07|14:35
uart_regs.cmp.logdb4.00 B02-04-07|14:34
uart_regs.cmp.rdb43.15 kB02-04-07|14:35
uart_regs.cmp.tdb82.48 kB02-04-07|14:35
uart_regs.cmp0.ddb107.28 kB02-04-07|14:35
uart_regs.db_info136.00 B29-03-07|14:56
uart_regs.eco.cdb141.00 B02-04-07|15:35
uart_regs.fit.qmsg79.56 kB02-04-07|14:35
uart_regs.hier_info40.59 kB02-04-07|14:34
uart_regs.hif15.64 kB02-04-07|14:34
uart_regs.map.cdb33.94 kB02-04-07|14:34
uart_regs.map.hdb20.18 kB02-04-07|14:34
uart_regs.map.logdb4.00 B02-04-07|14:34
uart_regs.map.qmsg42.39 kB02-04-07|14:34
uart_regs.pre_map.cdb37.15 kB02-04-07|14:34
uart_regs.pre_map.hdb26.27 kB02-04-07|14:34
uart_regs.psp0.00 B02-04-07|14:34
uart_regs.rtlv.hdb26.13 kB02-04-07|14:34
uart_regs.rtlv_sg.cdb40.99 kB02-04-07|14:34
uart_regs.rtlv_sg_swap.cdb3.98 kB02-04-07|14:34
uart_regs.sgdiff.cdb30.69 kB02-04-07|14:34
uart_regs.sgdiff.hdb28.27 kB02-04-07|14:34
uart_regs.signalprobe.cdb871.00 B02-04-07|14:35
uart_regs.sld_design_entry.sci135.00 B02-04-07|15:35
uart_regs.sld_design_entry_dsc.sci135.00 B02-04-07|14:34
uart_regs.syn_hier_info0.00 B02-04-07|14:34
uart_regs.tan.qmsg87.97 kB02-04-07|14:35
uart_regs_cmp.qrpt0.00 B31-12-04|13:01
uart_regs_hier_info42.23 kB31-12-04|13:39
uart_regs_sim.qrpt0.00 B31-12-04|13:40
uart_regs_syn_hier_info0.00 B31-12-04|13:35
sim.cfg4.00 B31-12-04|13:44
uart_regs.asm.rpt5.63 kB02-04-07|14:35
uart_regs.done26.00 B02-04-07|14:35
uart_regs.fit.eqn139.37 kB02-04-07|14:35
uart_regs.fit.rpt260.92 kB02-04-07|14:35
uart_regs.fit.summary517.00 B02-04-07|14:35
uart_regs.fld85.00 B14-01-05|23:31
uart_regs.flow.rpt3.73 kB02-04-07|14:35
uart_regs.map.eqn115.82 kB02-04-07|14:34
uart_regs.map.rpt73.93 kB02-04-07|14:34
uart_regs.map.summary429.00 B02-04-07|14:34
uart_regs.pin76.46 kB02-04-07|14:35
uart_regs.pof512.14 kB31-12-04|13:37
uart_regs.qpf1.53 kB15-01-05|21:30
uart_regs.qsf3.85 kB02-04-07|14:30
uart_regs.qws1.14 kB02-04-07|15:35
uart_regs.rbf433.62 kB31-12-04|13:37
uart_regs.sim.rpt11.63 kB14-01-05|21:32
uart_regs.sof418.99 kB31-12-04|13:37
uart_regs.tan.rpt358.38 kB02-04-07|14:35
uart_regs.tan.summary2.22 kB02-04-07|14:35
uart_regs_assignment_defaults.qdf34.14 kB29-03-07|14:56
db0.00 B13-10-08|20:22
funcsim0.00 B13-10-08|20:22
parsim0.00 B13-10-08|20:22
sch0.00 B13-10-08|20:22
db0.00 B13-10-08|20:22
db0.00 B13-10-08|20:22
sim0.00 B13-10-08|20:22
src0.00 B13-10-08|20:22
core0.00 B13-10-08|20:22
dev0.00 B13-10-08|20:22
...
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UART Verilog sorce code and Simulation code and FIFO code (1.09 MB)

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